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21. 发明授权

US06211003B1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06211003B1
公开(公告)日：2001-04-03
申请号：US09270685
申请日：1999-03-16
申请人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
发明人： Yasuhiro Taniguchi , Shoji Shukuri , Kenichi Kuroda , Shuji Ikeda , Takashi Hashimoto
IPC分类号： H01L218238
CPC分类号： H01L27/11526 , H01L21/76229 , H01L21/76237 , H01L21/823892 , H01L27/0214 , H01L27/10894 , H01L27/10897 , H01L27/11546
摘要： A photoresist pattern through which a first well forming region and a second well forming region are exposed is formed over a semiconductor substrate, used as the mask to dope the semiconductor substrate with an impurity thereby to form buried n-wells, and further used as the mask to dope the same with an impurity thereby to form shallow p-wells in a self-alignment manner over the buried n-wells. Subsequently, the photoresist pattern is removed. After this, a photoresist pattern through which the outer peripheral region of the first well forming region and a third well forming region are exposed is formed over the major surface of the semiconductor substrate, and used as the mask to dope the semiconductor substrate with an impurity thereby to form shallow p-wells.
摘要翻译：在半导体衬底上形成第一阱形成区域和第二阱形成区域暴露的光致抗蚀剂图案，用作掩模以掺杂杂质从而形成掩埋的n阱，并进一步用作掩模用杂质掺杂，从而在掩埋的n阱上以自对准的方式形成浅的p阱。随后，去除光致抗蚀剂图案。之后，在半导体衬底的主表面上形成有暴露第一阱形成区域和第三阱形成区域的外周区域的光致抗蚀剂图案，并用作掩模以掺杂杂质的半导体衬底从而形成浅的p阱。

22. 发明授权

US08304820B2 Semiconductor device utilizing dummy gate to enhance processing precision 有权
标题翻译：半导体器件利用虚拟栅极提高加工精度
公开(公告)号：US08304820B2
公开(公告)日：2012-11-06
申请号：US13304350
申请日：2011-11-24
申请人： Hideaki Yamakoshi , Hideyuki Yashima , Shinichiro Abe , Yasuhiro Taniguchi
发明人： Hideaki Yamakoshi , Hideyuki Yashima , Shinichiro Abe , Yasuhiro Taniguchi
IPC分类号： H01L29/76
CPC分类号： H01L27/11575 , H01L27/11546 , H01L27/11548
摘要： Processing of memory cells forming a nonvolatile memory in a semiconductor device. A second polysilicon film is formed in such a manner as to cover a first polysilicon film and a dummy gate electrode. Thus, the second polysilicon film is formed reflecting the shapes of a step difference portion and a gap groove. Particularly, in the second polysilicon film covering the gap groove, a concave part is formed. Subsequently, over the second polysilicon film, an antireflection film is formed. Thus, the antireflection film having high flowability flows from the higher region to the lower region of the step difference portion, but is stored in a sufficient amount in the concave part. Accordingly, the antireflection film is supplied from the concave part so as to compensate for the amount of the antireflection film to flow out therefrom.
摘要翻译：在半导体器件中形成非易失性存储器的存储单元的处理。以覆盖第一多晶硅膜和虚拟栅电极的方式形成第二多晶硅膜。因此，第二多晶硅膜形成为反映台阶差部分和间隙凹槽的形状。特别地，在覆盖间隙槽的第二多晶硅膜中，形成凹部。接着，在第二多晶硅膜上形成防反射膜。因此，具有高流动性的防反射膜从台阶差部分的较高区域流向下部区域，但是在凹部中以足够的量储存。因此，从凹部供给防反射膜，以补偿从其中流出的防反射膜的量。

23. 发明授权

US07601581B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07601581B2
公开(公告)日：2009-10-13
申请号：US11649759
申请日：2007-01-05
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
摘要翻译：提供一种半导体器件的制造方法，其包括在半导体衬底上形成栅极绝缘膜，电荷存储膜，绝缘膜，多晶硅膜，氧化硅膜，氮化硅膜和帽绝缘膜的膜堆叠; 通过光刻和蚀刻从低击穿电压MISFET形成区域和高击穿电压MISFET形成区域去除膜堆叠; 在半导体衬底上形成栅极绝缘膜，多晶硅膜和帽绝缘膜，在低击穿电压MISFET形成区域和高击穿电压MISFET形成区域中形成栅电极，然后在存储器单元形成区域中形成栅电极。通过以不同的步骤形成第一MISFET和第二MISFET的栅极的半导体器件的制造技术，本发明使得可以提供具有改善的可靠性的第一MISFET和第二MISFET。

24. 发明授权

US07550809B2 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
标题翻译：具有用于栅绝缘的沉积层的半导体集成电路器件
公开(公告)号：US07550809B2
公开(公告)日：2009-06-23
申请号：US11848992
申请日：2007-08-31
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/62 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.
摘要翻译：一种半导体集成电路器件的制造方法，包括：第一场效应晶体管，其具有在半导体衬底的主表面的第一元件形成区域上形成的栅极绝缘膜; 以及第二场效应晶体管，其具有形成在所述半导体衬底的主表面的第二元件形成区域上并且比所述第一场效应晶体管的栅极绝缘膜更薄的栅极绝缘膜。该方法包括以下步骤：在半导体衬底的主表面的第一元件形成区域和第二元件形成区域上形成热氧化膜; 在包括所述热氧化膜的半导体衬底的主表面上形成沉积膜; 从所述第二元件形成区域上方去除所述沉积膜和所述热氧化膜; 以及在所述第二元件形成区域上形成热氧化膜，以在所述第一元件形成区域和所述第二元件形成区域上分别形成栅极绝缘膜。

25. 发明申请

US20070207575A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20070207575A1
公开(公告)日：2007-09-06
申请号：US11649759
申请日：2007-01-05
申请人： Yasuhiro Taniguchi , Kazuyoshi Shiba
发明人： Yasuhiro Taniguchi , Kazuyoshi Shiba
IPC分类号： H01L21/8238
CPC分类号： H01L21/823462 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11568 , H01L27/11573
摘要： Provided is a manufacturing method of a semiconductor device, which comprises forming a film stack of a gate insulating film, a charge storage film, insulating film, polysilicon film, silicon oxide film, silicon nitride film and cap insulating film over a semiconductor substrate; removing the film stack by photolithography and etching from a low breakdown voltage MISFET formation region and a high breakdown voltage MISFET formation region; forming gate insulating films, polysilicon film and cap insulating film over the semiconductor substrate, forming a gate electrode in the low breakdown voltage MISFET formation region and high breakdown voltage MISFET formation region, and then forming a gate electrode in a memory cell formation region. By the manufacturing technology of a semiconductor device for forming the gate electrodes of a first MISFET and a second MISFET in different steps, the present invention makes it possible to provide the first MISFET and the second MISFET each having improved reliability.
摘要翻译：提供一种半导体器件的制造方法，其包括在半导体衬底上形成栅极绝缘膜，电荷存储膜，绝缘膜，多晶硅膜，氧化硅膜，氮化硅膜和帽绝缘膜的膜堆叠; 通过光刻和蚀刻从低击穿电压MISFET形成区域和高击穿电压MISFET形成区域去除膜堆叠; 在半导体衬底上形成栅极绝缘膜，多晶硅膜和帽绝缘膜，在低击穿电压MISFET形成区域和高击穿电压MISFET形成区域中形成栅电极，然后在存储器单元形成区域中形成栅电极。通过以不同的步骤形成第一MISFET和第二MISFET的栅极的半导体器件的制造技术，本发明使得可以提供具有改善的可靠性的第一MISFET和第二MISFET。

26. 发明授权

US07023062B2 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
公开(公告)号：US07023062B2
公开(公告)日：2006-04-04
申请号：US10635511
申请日：2003-08-07
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L29/76
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

27. 发明申请

US20050245045A1 Semiconductor integrated circuit device having deposited layer for gate insulation 有权
标题翻译：具有用于栅绝缘的沉积层的半导体集成电路器件
公开(公告)号：US20050245045A1
公开(公告)日：2005-11-03
申请号：US11178375
申请日：2005-07-12
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L21/8247 , H01L21/316 , H01L21/76 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.
摘要翻译：一种半导体集成电路器件的制造方法，包括：第一场效应晶体管，其具有在半导体衬底的主表面的第一元件形成区域上形成的栅极绝缘膜; 以及第二场效应晶体管，其具有形成在所述半导体衬底的主表面的第二元件形成区域上并且比所述第一场效应晶体管的栅极绝缘膜更薄的栅极绝缘膜。该方法包括以下步骤：在半导体衬底的主表面的第一元件形成区域和第二元件形成区域上形成热氧化膜; 在包括所述热氧化膜的半导体衬底的主表面上形成沉积膜; 从所述第二元件形成区域上方去除所述沉积膜和所述热氧化膜; 以及在所述第二元件形成区域上形成热氧化膜，以在所述第一元件形成区域和所述第二元件形成区域上分别形成栅极绝缘膜。

28. 发明授权

US06842376B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06842376B2
公开(公告)日：2005-01-11
申请号：US10638491
申请日：2003-08-12
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C16/06 , G11C8/08 , G11C16/02 , G11C16/12 , G11C16/34 , G11C16/04
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

29. 发明授权

US06646313B2 Semiconductor integrated circuit device and having deposited layer for gate insulation 有权
公开(公告)号：US06646313B2
公开(公告)日：2003-11-11
申请号：US09961360
申请日：2001-09-25
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L2976
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.

30. 发明授权

US06376316B2 Method for manufacturing semiconductor integrated circuit device having deposited layer for gate insulation 有权
标题翻译：具有用于栅极绝缘的沉积层的半导体集成电路器件的制造方法
公开(公告)号：US06376316B2
公开(公告)日：2002-04-23
申请号：US09208019
申请日：1998-12-09
申请人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
发明人： Shoji Shukuri , Norio Suzuki , Yasuhiro Taniguchi
IPC分类号： H01L218234
CPC分类号： H01L21/823456 , H01L21/28185 , H01L21/28194 , H01L21/823462 , H01L21/823481 , H01L21/8238 , H01L21/823857 , H01L21/823878 , H01L27/0922 , H01L27/105 , H01L27/1052 , H01L27/10873 , H01L27/10894 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L29/513 , H01L29/6659 , H01L29/7833
摘要： A method for manufacturing a semiconductor integrated circuit device including a first field effect transistor having a gate insulating film formed over a first element forming region of a main surface of a semiconductor substrate; and a second field effect transistor having a gate insulating film formed over a second element forming region of the main surface of the semiconductor substrate and made thinner than the gate insulating film of the first field effect transistor. The method comprises the steps of forming a thermally oxidized film over a first element forming region and a second element forming region of the main surface of the semiconductor substrate; forming a deposited film over the main surface of the semiconductor substrate including said thermally oxidized film; removing the deposited film and said thermally oxidized film from over the second element forming region; and forming a thermally oxidized film over the second element forming region to form a gate insulating film individually over the first element forming region and the second element forming region.
摘要翻译：一种半导体集成电路器件的制造方法，该半导体集成电路器件包括在半导体衬底的主表面的第一元件形成区域上形成有栅极绝缘膜的第一场效应晶体管; 以及第二场效应晶体管，其具有形成在所述半导体衬底的主表面的第二元件形成区域上并且比所述第一场效应晶体管的栅极绝缘膜更薄的栅极绝缘膜。该方法包括以下步骤：在半导体衬底的主表面的第一元件形成区域和第二元件形成区域上形成热氧化膜; 在包括所述热氧化膜的半导体衬底的主表面上形成沉积膜; 从所述第二元件形成区域上方去除所述沉积膜和所述热氧化膜; 以及在所述第二元件形成区域上形成热氧化膜，以在所述第一元件形成区域和所述第二元件形成区域上分别形成栅极绝缘膜。

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