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21. 发明授权

US08686488B2 Nonvolatile semiconductor memory device and method of manufacturing the same 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US08686488B2
公开(公告)日：2014-04-01
申请号：US13602634
申请日：2012-09-04
申请人： Masaki Kondo , Nobutoshi Aoki , Takashi Izumida , Tomomi Yoda
发明人： Masaki Kondo , Nobutoshi Aoki , Takashi Izumida , Tomomi Yoda
IPC分类号： H01L29/788 , H01L21/4763
CPC分类号： H01L29/788 , H01L21/28273 , H01L27/11521 , H01L29/4916 , H01L29/66825 , H01L29/7883
摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a floating gate electrode formed on the gate insulating film, made of polysilicon containing a p-type impurity as a group XIII element, and having a lower film and an upper film stacked on the lower film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film. One of a concentration and an activation concentration of the p-type impurity in the upper film is higher than one of a concentration and an activation concentration of the p-type impurity in the lower film.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的栅绝缘膜，形成在栅极绝缘膜上的浮栅，由含有p型杂质的多晶硅组成，并且具有层叠在下膜上的下膜和上膜，形成在浮栅上的电极间绝缘膜和形成在电极间绝缘膜上的控制栅电极。上膜中的p型杂质的浓度和活化浓度之一高于下膜中的p型杂质的浓度和活化浓度之一。

22. 发明授权

US08487364B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
公开(公告)号：US08487364B2
公开(公告)日：2013-07-16
申请号：US12792378
申请日：2010-06-02
申请人： Takayuki Okamura , Noboru Ooike , Wataru Sakamoto , Takashi Izumida
发明人： Takayuki Okamura , Noboru Ooike , Wataru Sakamoto , Takashi Izumida
IPC分类号： H01L29/792 , H01L21/3205 , H01L21/4763
摘要： A nonvolatile semiconductor memory device according to embodiment includes: a semiconductor substrate having an upper portion being partitioned into a plurality of semiconductor portions extending in a first direction; a charge storage film provided on the semiconductor portion; a word-line electrode provided on the semiconductor substrate and extending in a second direction intersecting with the first direction; and a pair of selection gate electrodes provided on both sides of the word-line electrode in the first direction on the semiconductor substrate and extending in the second direction, a shortest distance between a corner portion of each of the semiconductor portions and each of the selection gate electrodes being longer than a shortest distance between the corner portion of the semiconductor portion and the word-line electrode in a cross section parallel to the second direction.

23. 发明授权

US08420467B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08420467B2
公开(公告)日：2013-04-16
申请号：US13224449
申请日：2011-09-02
申请人： Takashi Izumida , Nobutoshi Aoki
发明人： Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L21/8224
CPC分类号： H01L29/7851 , H01L29/1054 , H01L29/66795
摘要： A semiconductor device has a semiconductor substrate, a semiconductor fin which is formed on the semiconductor substrate, which has a long side direction and a short side direction, and which has a carbon-containing silicon film including an impurity and a silicon film formed on the carbon-containing silicon film, a gate electrode which is formed to face both side surfaces of the semiconductor fin in the short side direction, source and drain regions which are respectively formed in the semiconductor fin located in the direction of both sides in the long side direction of the semiconductor fin so as to sandwich the gate electrode, and an element isolation insulating film which is formed on the side surface of the semiconductor fin and between the gate electrode and the semiconductor substrate.
摘要翻译：半导体器件具有半导体衬底，形成在半导体衬底上的具有长边方向和短边方向的半导体鳍片，并且具有包含杂质的含碳硅膜和形成在其上的硅膜含碳硅膜，形成为在短边方向上面对半导体翅片的两侧面的栅电极，分别形成在长边方向两侧的半导体翅片中的源区和漏区半导体鳍片的方向以夹着栅极电极;以及元件隔离绝缘膜，其形成在半导体鳍片的侧表面上以及栅电极和半导体衬底之间。

24. 发明授权

US07986000B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07986000B2
公开(公告)日：2011-07-26
申请号：US12564349
申请日：2009-09-22
申请人： Makoto Mizukami , Kiyohito Nishihara , Masaki Kondo , Takashi Izumida , Hirokazu Ishida , Atsushi Fukumoto , Fumiki Aiso , Daigo Ichinose , Tadashi Iguchi
发明人： Makoto Mizukami , Kiyohito Nishihara , Masaki Kondo , Takashi Izumida , Hirokazu Ishida , Atsushi Fukumoto , Fumiki Aiso , Daigo Ichinose , Tadashi Iguchi
IPC分类号： H01L29/76 , H01L21/00 , H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11521 , H01L27/11524
摘要： A semiconductor device is formed on a SOI substrate having a semiconductor substrate, a buried oxide film formed on the semiconductor substrate, and a semiconductor layer formed on the buried oxide film, the semiconductor substrate having a first conductive type, the semiconductor layer having a second conductive type, wherein the buried oxide film has a first opening opened therethrough for communicating the semiconductor substrate with the semiconductor layer, the semiconductor layer is arranged to have a first buried portion buried in the first opening in contact with the semiconductor substrate and a semiconductor layer main portion positioned on the first buried portion and on the buried oxide film, the semiconductor substrate has a connection layer buried in a surface of the semiconductor substrate and electrically connected to the first buried portion in the first opening, the connection layer having the second conductive type, and the semiconductor device includes a contact electrode buried in a second opening, a side surface of the contact electrode being connected to the semiconductor layer main portion, a bottom surface of the contact electrode being connected to the connection layer, the second opening passing through the semiconductor layer main portion and the buried oxide film, and the second opening reaching a surface portion of the connection layer.
摘要翻译：半导体器件形成在具有半导体衬底的SOI衬底上，形成在半导体衬底上的掩埋氧化膜以及形成在掩埋氧化膜上的半导体层，该半导体衬底具有第一导电类型，该半导体层具有第二导电型导电型，其中所述掩埋氧化物膜具有通过其开口的第一开口，用于使所述半导体衬底与所述半导体层连通，所述半导体层被布置为具有埋在所述第一开口中的与所述半导体衬底接触的第一掩埋部分和半导体层主要部分位于第一掩埋部分和掩埋氧化膜上，半导体衬底具有埋在半导体衬底的表面中并与第一开口中的第一掩埋部分电连接的连接层，连接层具有第二导电类型，并且半导体器件包括接触电极阴极埋入第二开口中，接触电极的侧表面连接到半导体层主体部分，接触电极的底表面连接到连接层，第二开口穿过半导体层主体部分和埋设氧化膜，第二开口到达连接层的表面部分。

25. 发明申请

US20100295112A1 SEMICONDUCTOR STORAGE DEVICE 失效
标题翻译：半导体存储设备
公开(公告)号：US20100295112A1
公开(公告)日：2010-11-25
申请号：US12721757
申请日：2010-03-11
申请人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Takahisa Kanemura
发明人： Takashi Izumida , Nobutoshi Aoki , Masaki Kondo , Takahisa Kanemura
IPC分类号： H01L27/115
CPC分类号： H01L21/28273 , H01L27/11521 , H01L29/42324 , H01L29/66825 , H01L29/7883
摘要： A semiconductor storage device has a semiconductor substrate, a plurality of first insulating films formed on the semiconductor substrate with predetermined spacing therebetween, an element isolation region formed between the first insulating films in a first direction, a floating gate electrode comprising a first charge accumulation film formed on the first insulating film, a second charge accumulation film formed on the first charge accumulation film and having a width in a second direction orthogonal to the first direction smaller than the width of the first charge accumulation film, and a third charge accumulation film formed on the second charge accumulation film and having the width in the second direction larger than the width of the second charge accumulation film, a second insulating film formed on the second charge accumulation film and between the second charge accumulation film and the element isolation region, a third insulating film formed on the charge accumulation film and the element isolation region along the second direction, and a control gate electrode formed on the third insulating film.
摘要翻译：半导体存储装置具有半导体基板，在半导体基板上形成有规定间隔的多个第一绝缘膜，在第一方向上形成在第一绝缘膜之间的元件隔离区域，包括第一电荷累积膜的浮栅电极形成在所述第一绝缘膜上的第二电荷累积膜，形成在所述第一电荷累积膜上并且具有与所述第一方向正交的第二方向的宽度小于所述第一电荷累积膜的宽度的第二电荷累积膜，以及形成的第三电荷累积膜在第二电荷累积膜上并且具有大于第二电荷累积膜的宽度的第二方向的宽度，形成在第二电荷累积膜上以及在第二电荷累积膜和元件隔离区之间的第二绝缘膜，形成在电荷累积膜上的第三绝缘膜和沿着第二方向的元件隔离区域，以及形成在第三绝缘膜上的控制栅极电极。

26. 发明申请

US20090146203A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090146203A1
公开(公告)日：2009-06-11
申请号：US12327418
申请日：2008-12-03
申请人： Takashi Izumida , Masaki Kondo
发明人： Takashi Izumida , Masaki Kondo
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G11C16/0483 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42324
摘要： In one aspect of the present invention, a nonvolatile semiconductor memory device may include a semiconductor substrate; a plurality of tunnel insulating films formed on the semiconductor substrate at predetermined intervals in a first direction; a plurality of floating gate electrodes each having a first portion and a second portion, the first portions being formed on the respective tunnel insulating films, the second portions being formed on the respective first portions and having smaller width than the first portions in the first direction; an inter-gate insulating film formed on the floating gate electrodes; and first and second control gate electrodes respectively formed on sidewalls, in the first direction, of the second portion of each of the plurality of floating gate electrodes with the inter-gate insulating film interposed therebetween.
摘要翻译：在本发明的一个方面中，非易失性半导体存储器件可以包括半导体衬底; 在第一方向上以预定间隔形成在所述半导体衬底上的多个隧道绝缘膜; 多个浮置栅极，每个具有第一部分和第二部分，所述第一部分形成在相应的隧道绝缘膜上，所述第二部分形成在相应的第一部分上，并且具有比所述第一方向上的第一部分更小的宽度 ; 形成在所述浮栅电极上的栅极间绝缘膜; 以及第一和第二控制栅极电极，分别形成在多个浮置栅电极中的每一个的第二部分的第一方向的侧壁上，栅间绝缘膜插入其间。

27. 发明申请

US20090101959A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20090101959A1
公开(公告)日：2009-04-23
申请号：US12248449
申请日：2008-10-09
申请人： Takahisa KANEMURA , Takashi Izumida , Nobutoshi Aoki
发明人： Takahisa KANEMURA , Takashi Izumida , Nobutoshi Aoki
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor memory device including: a semiconductor substrate; memory cell transistors that are series-connected; and a select transistor that includes: a first diffusion region that is formed in the semiconductor substrate at one end of the memory cell transistors; a first insulating film that is formed on the semiconductor substrate at a side of the first diffusion region; a select gate electrode that is formed on the first insulating film; a semiconductor pillar that is formed to extend upward from the semiconductor substrate and to be separated from the select gate electrode; a second insulating film that is formed between the select gate electrode and the semiconductor pillar; and a second diffusion region that is formed on the semiconductor pillar.
摘要翻译：根据本发明的一个方面，提供了一种非易失性半导体存储器件，包括：半导体衬底; 串联连接的存储单元晶体管; 以及选择晶体管，其包括：在所述存储单元晶体管的一端形成在所述半导体衬底中的第一扩散区域; 在所述第一扩散区域的一侧形成在所述半导体基板上的第一绝缘膜; 形成在所述第一绝缘膜上的选择栅电极; 形成为从半导体衬底向上延伸并与选择栅电极分离的半导体柱; 形成在选择栅电极和半导体柱之间的第二绝缘膜; 以及形成在所述半导体柱上的第二扩散区域。

28. 发明授权

US07473964B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07473964B2
公开(公告)日：2009-01-06
申请号：US11713803
申请日：2007-03-05
申请人： Takashi Izumida
发明人： Takashi Izumida
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/6659 , H01L29/7843
摘要： A semiconductor device includes: an insulating layer; a semiconductor fin protruding from the insulating layer, extending in a first direction parallel to a major surface of the insulating layer, and having a source region, a channel section, and a drain region arranged in the first direction; a gate electrode opposed at least to a side face of the channel section in the semiconductor fin and extending in a second direction that is substantially orthogonal to the first direction and parallel to the major surface of the insulating layer; an insulating film interposed between the semiconductor fin and the gate electrode; a spacer layer provided on the channel section; a sidewall insulating layer provided adjacent to a side face of the spacer layer substantially parallel to the second direction; and a stress liner. The stress liner covers the sidewall insulating layer and the spacer layer and has an intrinsic stress for distorting the semiconductor fin. The sidewall insulating layer has a thickness of 45 nanometers (nm) or more in the first direction, and the spacer layer has a height of 105 nanometers (nm) or more.
摘要翻译：半导体器件包括：绝缘层; 从所述绝缘层突出的半导体鳍片，沿着与所述绝缘层的主表面平行的第一方向延伸，并且具有沿所述第一方向排列的源极区域，沟道部分和漏极区域; 至少与所述半导体鳍片中的沟道部分的侧面相对且在与所述第一方向大致正交且平行于所述绝缘层的主表面的第二方向上延伸的栅电极; 介于所述半导体鳍片和所述栅电极之间的绝缘膜; 设置在通道部分上的间隔层; 侧壁绝缘层，设置成与所述间隔层的与所述第二方向大致平行的侧面相邻; 和应力衬垫。应力衬垫覆盖侧壁绝缘层和间隔层，并且具有使半导体翅片变形的固有应力。侧壁绝缘层在第一方向上具有45纳米（nm）以上的厚度，间隔层的高度为105纳米（nm）以上。

29. 发明申请

US20080246072A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20080246072A1
公开(公告)日：2008-10-09
申请号：US11773721
申请日：2007-07-05
申请人： Masaki Kondo , Takashi Izumida , Nobutoshi Aoki , Toshiharu Watanabe
发明人： Masaki Kondo , Takashi Izumida , Nobutoshi Aoki , Toshiharu Watanabe
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11524
摘要： In a nonvolatile semiconductor memory device including a memory cell column formed by connecting in series a plurality of memory cells each having a structure in which a charge-storage layer and a control gate are stacked via an insulating layer on a semiconductor substrate, a first selection transistor formed on the semiconductor substrate and connected between one end of the memory cell column and a common source line, and a second selection transistor formed on the semiconductor substrate and connected between the other end of the memory cell column and a bit line, a recessed portion is formed on a surface of the semiconductor substrate between the first selection transistor and a memory cell adjacent to the first selection transistor, and an edge at a side of the first selection transistor in the recessed portion reaches an end portion at a side of the memory cell in a gate of the first selection transistor.
摘要翻译：在包括存储单元列的非易失性半导体存储器件中，该存储单元列是通过串联连接多个存储单元而形成的，每个存储单元具有通过绝缘层在半导体衬底上层叠电荷存储层和控制栅极的结构，第一选择形成在半导体衬底上并连接在存储单元列的一端和公共源极线之间的晶体管，以及形成在半导体衬底上并连接在存储单元列的另一端和位线之间的第二选择晶体管，部分形成在第一选择晶体管和与第一选择晶体管相邻的存储单元之间的半导体衬底的表面上，并且凹陷部分中的第一选择晶体管的一侧的边缘到达第二选择晶体管的一侧的端部第一选择晶体管的栅极中的存储单元。

30. 发明申请

US20070158720A1 Semiconductor device with cells each having a trench capacitor and a switching transistor thereon 审中-公开
标题翻译：具有各自具有沟槽电容器和其上的开关晶体管的单元的半导体器件
公开(公告)号：US20070158720A1
公开(公告)日：2007-07-12
申请号：US11408966
申请日：2006-04-24
申请人： Takashi Izumida
发明人： Takashi Izumida
IPC分类号： H01L29/94
CPC分类号： H01L27/10832 , H01L21/84 , H01L27/10867 , H01L27/1087
摘要： A semiconductor device includes a semiconductor substrate, at least one trench capacitor which is buried into the surface area of the semiconductor substrate, and a first insulation film which is formed on the trench capacitor. The semiconductor device further includes at least one switching transistor provided on the surface of the semiconductor substrate which corresponds to the trench capacitor, the switching transistor having a body section set in an electrically floating state between source and drain regions, the first insulation film being interposed between the body section of the switching transistor and the trench capacitor opposed to one another, the trench capacitor being electrically connected to one of the source and drain regions of the switching transistor.
摘要翻译：半导体器件包括半导体衬底，埋入半导体衬底的表面区域中的至少一个沟槽电容器和形成在沟槽电容器上的第一绝缘膜。半导体器件还包括至少一个开关晶体管，其设置在半导体衬底的与沟槽电容器相对应的表面上，开关晶体管具有在源极和漏极区域之间设置为电浮置状态的主体部分，第一绝缘膜插入在开关晶体管的主体部分和沟槽电容器彼此相对的沟槽电容器之间，沟槽电容器电连接到开关晶体管的源极和漏极区域之一。

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