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21. 发明授权

US06373774B1 Semiconductor memory device with bank configuration 有权
公开(公告)号：US06373774B1
公开(公告)日：2002-04-16
申请号：US09773710
申请日：2001-02-02
申请人： Masatoshi Ishikawa , Katsumi Dosaka
发明人： Masatoshi Ishikawa , Katsumi Dosaka
IPC分类号： G11C800
摘要： The semiconductor memory device includes a logic circuit and a memory macro. The memory macro has a region in which memory blocks are formed. Memory spaces are increased in a predetermined order. Address connection lines connecting between the logic circuit and the memory macro alter a connecting relation such that consecutive addresses are realized in each bank. A word line address specified by the logic circuit is used in the memory macro with no change therein.

22. 发明授权

US6091659A Synchronous semiconductor memory device with multi-bank configuration 失效
标题翻译：具有多组配置的同步半导体存储器件
公开(公告)号：US6091659A
公开(公告)日：2000-07-18
申请号：US318433
申请日：1999-05-25
申请人： Naoya Watanabe , Katsumi Dosaka
发明人： Naoya Watanabe , Katsumi Dosaka
IPC分类号： G11C11/407 , G11C7/10 , G11C8/16 , G11C11/401 , G11C11/409 , G11C8/00
CPC分类号： G11C8/16 , G11C7/1006
摘要： Memory blocks provided to share a sense amplifier band, a global IO (GIOB) bus provided in common to the memory blocks for transferring internal data, and local IO bus lines provided corresponding to the memory blocks are connection-controlled based on signals related to a column select operation. Driving memory blocks independently from each other permits each memory block to be used as a bank, and if one memory block is accessed during activation of another memory block, data can be prevented from colliding on the global IO bus. A main memory with high page hit rate is implemented using a semiconductor memory device with a shared-sense amplifier configuration. When a memory block sharing a sense amplifier coupled to another memory block is addressed, the another memory block is inactivated and then addressed memory block is accessed, when a valid data is output, such valid data outputting is signaled by a data valid signal.
摘要翻译：提供用于共享读出放大器频带的存储器块，共同提供用于传送内部数据的存储器块的全局IO（GIOB）总线以及与存储器块相对应地提供的本地IO总线的连接控制是基于与列选择操作。彼此独立地驱动存储器块允许每个存储器块用作存储体，并且如果在激活另一个存储器块期间访问一个存储器块，则可以防止数据在全局IO总线上冲突。具有高页命中率的主存储器使用具有共享读出放大器配置的半导体存储器件来实现。当共享耦合到另一个存储器块的读出放大器的存储器块被寻址时，另一个存储块被去激活，然后寻址存储器块被访问，当输出有效数据时，这样的有效数据输出由数据有效信号发出。

23. 发明授权

US5835448A Clock synchronous semiconductor memory device for determining an operation mode 失效
标题翻译：用于确定操作模式的时钟同步半导体存储器件
公开(公告)号：US5835448A
公开(公告)日：1998-11-10
申请号：US880153
申请日：1997-06-20
申请人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
发明人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
IPC分类号： G11C11/41 , G06F12/08 , G11C7/10 , G11C7/22 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1072 , G11C11/005 , G11C11/4076 , G11C11/4096 , G11C7/103 , G11C7/1051 , G11C7/22
摘要： A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.
摘要翻译：当外部时钟信号Ka处于非活动状态时，信号输入缓冲器达到通过状态，并且响应于外部信号产生内部信号，并且当外部时钟信号处于非活动状态时，信号输入缓冲器达到锁存状态。响应于正在使用的从属数据寄存器的检测，执行从通过从属数据寄存器将数据存储在DRAM阵列中的主数据寄存器的数据传送。从数据寄存器存储要传输到SRAM阵列的数据或要外部访问的数据。因此，提供了可高速访问并且不等待的同步半导体存储器件。此外，响应于外部时钟信号的激活，内部时钟信号被激活预定时间以确保精确的内部操作定时。

24. 发明授权

US5774409A Multi-bank dRAM suitable for integration with processor on common semiconductor chip 失效
标题翻译：多组dRAM适合与公共半导体芯片上的处理器集成
公开(公告)号：US5774409A
公开(公告)日：1998-06-30
申请号：US797081
申请日：1997-02-10
申请人： Akira Yamazaki , Katsumi Dosaka
发明人： Akira Yamazaki , Katsumi Dosaka
IPC分类号： G06F12/08 , G06F12/00 , G06F12/02 , G06F12/06 , G11C8/12 , G11C11/401 , G11C11/406 , G11C11/407 , G11C11/408 , G11C11/409
CPC分类号： G11C8/12 , G06F12/0215 , G06F12/0893 , Y02B60/1225
摘要： A dynamic random access memory DRAM includes banks which are driven to active or inactive states independently of each other. Activation/inactivation of these banks are controlled by row controllers operating independently of each other, whereby a page or word line can be selected in each of the banks, a page hit rate can be increased, and the number of array precharge operation times in a page error as well as power consumption can be reduced in response. Thus, the cache hit rate of a processor having a built-in DRAM is increased and power consumption is reduced.
摘要翻译：动态随机存取存储器DRAM包括彼此独立地被驱动到活动或非活动状态的存储体。这些组的激活/失活由彼此独立地操作的行控制器控制，从而可以在每个存储体中选择页面或字线，可以增加页面命中率，并且在一个或多个存储器中的阵列预充电操作次数可以减少页面错误以及功耗。因此，具有内置DRAM的处理器的高速缓存命中率增加并且功耗降低。

25. 发明授权

US5680363A Semiconductor memory capable of transferring data at a high speed between an SRAM and a DRAM array 失效
标题翻译：能够在SRAM和DRAM阵列之间高速传输数据的半导体存储器
公开(公告)号：US5680363A
公开(公告)日：1997-10-21
申请号：US632279
申请日：1996-04-15
申请人： Katsumi Dosaka , Masaki Kumanoya
发明人： Katsumi Dosaka , Masaki Kumanoya
IPC分类号： G06F12/08 , G06F12/00 , G11C7/00 , G11C7/10 , G11C11/401 , G11C11/407 , G11C11/409
CPC分类号： G11C7/103 , G11C7/1051 , G11C7/1078
摘要： In an operation of transferring data between a DRAM array and an SRAM array through a bidirectional transfer gate circuit, data blocks on a selected one in the DRAM array are sequentially selected in a high speed mode, word lines are sequentially selected in the SRAM array, so that data is transferred in a time division multiplexing manner between the DRAM array and the SRAM array in units of data block. A cache block size in a semiconductor memory device containing a cache can be externally changed depending on the application with the internal configuration maintained unchangedly.
摘要翻译：在通过双向传输门电路在DRAM阵列和SRAM阵列之间传送数据的操作中，DRAM阵列中所选择的数据块以高速模式顺序地选择，在SRAM阵列中依次选择字线，使得数据以数据块为单位在DRAM阵列和SRAM阵列之间以时分复用方式传送。包含缓存的半导体存储器件中的高速缓存块大小可以根据内部配置保持不变的应用而外部改变。

26. 发明授权

US5650968A Semiconductor memory device 失效
公开(公告)号：US5650968A
公开(公告)日：1997-07-22
申请号：US655322
申请日：1996-05-21
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

27. 发明授权

US5623454A Semiconductor memory device 失效
公开(公告)号：US5623454A
公开(公告)日：1997-04-22
申请号：US599265
申请日：1996-02-09
申请人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
发明人： Katsumi Dosaka , Masaki Kumanoya , Kouji Hayano , Akira Yamazaki , Hisashi Iwamoto , Hideaki Abe , Yasuhiro Konishi , Katsumitsu Himukashi , Yasuhiro Ishizuka , Tsukasa Saiki
IPC分类号： G06F12/08 , G11C7/00 , G11C7/10 , G11C7/22 , G11C8/00 , G11C8/12 , G11C11/00 , G11C13/00
CPC分类号： G11C8/00 , G11C11/005 , G11C11/4076 , G11C11/4097 , G11C11/413 , G11C7/10 , G11C7/1018 , G11C7/1045 , G11C7/22 , G11C8/12 , G06F12/0893 , G11C2207/002 , G11C2207/2227 , G11C2207/2245 , Y02B60/1225
摘要： A semiconductor memory device includes a DRAM, an SRAM and a bi-direction transfer gate circuit provided between SRAM and DRAM. SRAM array includes a plurality of sets of word lines. Each set is provided in each row of SRAM array and each word line in each set is connected to a different group of memory cells of an associated row. An address signal for the SRAM and an address signal for the DRAM are separately applied to an address buffer. The semiconductor memory device further includes an additional function control circuit for realizing a burst mode and a sleep mode. A data transfer path from DRAM to the SRAM and a data transfer path from the SRAM to the DRAM are separately provided in the bi-directional transfer gate circuit. Data writing paths and data reading paths are separately provided in the DRAM array. By the above described structure, operation of the buffer circuit is stopped in the sleep mode, reducing power consumption. Since data writing path and data reading path are separately provided in the DRAM array, addresses to the DRAM array can be applied in non-multiplexed manner, so that data can be transferred at high speed from the DRAM array to the SRAM array, enabling high speed operation even at a cache miss.

28. 发明授权

US5521878A Clock synchronous semiconductor memory device 失效
标题翻译：时钟同步半导体存储器件
公开(公告)号：US5521878A
公开(公告)日：1996-05-28
申请号：US305522
申请日：1994-09-12
申请人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
发明人： Jun Ohtani , Akira Yamazaki , Katsumi Dosaka
IPC分类号： G11C11/41 , G06F12/08 , G11C7/10 , G11C7/22 , G11C11/00 , G11C11/401 , G11C11/407 , G11C11/4076 , G11C11/409 , G11C11/4096 , G11C8/00
CPC分类号： G11C7/1072 , G11C11/005 , G11C11/4076 , G11C11/4096 , G11C7/103 , G11C7/1051 , G11C7/22
摘要： A signal input buffer attains a through state when an external clock signal Ka is in an inactive state and generates an internal signal in response to an external signal, and attains a latch state when the external clock signal is in an inactive state. Data transfer from a master data register which stores data in an DRAM array through a slave data register is executed in response to a detection of the slave data register of being in use. The slave data register stores data to be transferred to an SRAM array or data to be externally accessed. Thus, a synchronous semiconductor memory device accessible at a high speed and with no wait is provided. In addition, internal clock signal is activated for a predetermined time in response to activation of an external clock signal to secure a precise internal operating timing.
摘要翻译：当外部时钟信号Ka处于非活动状态时，信号输入缓冲器达到通过状态，并且响应于外部信号产生内部信号，并且当外部时钟信号处于非活动状态时，信号输入缓冲器达到锁存状态。响应于正在使用的从属数据寄存器的检测，执行从通过从属数据寄存器将数据存储在DRAM阵列中的主数据寄存器的数据传送。从数据寄存器存储要传输到SRAM阵列的数据或要外部访问的数据。因此，提供了可高速访问并且不等待的同步半导体存储器件。此外，响应于外部时钟信号的激活，内部时钟信号被激活预定时间以确保精确的内部操作定时。

29. 发明授权

US5184321A Semiconductor memory device comprising a plurality of memory arrays with improved peripheral circuit location and interconnection arrangement 失效
标题翻译：半导体存储器件包括具有改进的外围电路位置和互连布置的多个存储器阵列
公开(公告)号：US5184321A
公开(公告)日：1993-02-02
申请号：US821875
申请日：1992-01-16
申请人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Yasuhiro Konishi , Masaki Kumanoya , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/4074 , G11C11/408
CPC分类号： G11C11/4074 , G11C11/408 , Y10S257/92
摘要： A plurality of memory arrays (10a, 10b) are formed on a semiconductor chip (CH). A peripheral circuit (60) is arranged in the central portion of the plurality of memory arrays (10a, 10b). A plurality of pads (PD;p1.about.p18) are formed on both ends of the semiconductor chip (CH). The plurality of memory arrays (10a, 10b) are formed of predetermined layers (101.about.109). A plurality of interconnections (L) to be connected between the plurality of pads (PD;p1.about.p18) and the peripheral circuit (60) are provided to cross the plurality of memory arrays. The plurality of interconnections (L) are formed of layers (112;113) other than the predetermined ones.
摘要翻译：多个存储器阵列（10a，10b）形成在半导体芯片（CH）上。外围电路（60）布置在多个存储器阵列（10a，10b）的中心部分。在半导体芯片（CH）的两端形成有多个焊盘（PD; p1差异p18）。多个存储器阵列（10a，10b）由预定层形成（101差异109）。要连接在多个焊盘（PD; p1 DIFFERENCE p18）和外围电路（60）之间的多个互连（L）被设置成跨越多个存储器阵列。多个互连（L）由除预定的互连层之外的层（112; 113）形成。

30. 发明授权

US4961167A Substrate bias generator in a dynamic random access memory with auto/self refresh functions and a method of generating a substrate bias therein 失效
标题翻译：具有自动/自刷新功能的动态随机存取存储器中的衬底偏置发生器及其中产生衬底偏置的方法
公开(公告)号：US4961167A
公开(公告)日：1990-10-02
申请号：US381347
申请日：1989-07-18
申请人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
发明人： Masaki Kumanoya , Yasuhiro Konishi , Katsumi Dosaka , Takahiro Komatsu , Yoshinori Inoue
IPC分类号： G11C11/4074
CPC分类号： G11C11/4074
摘要： A dynamic random access memory with self-refresh function, which includes a substrate bias generator (100) adapted to be intermittently driven to apply a bias potential to a semiconductor substrate (15). This memory device comprises a circuit (91) for generating an internal refresh instruction signal (.phi..sub.S) in response to an external refresh instruction signal, a circuit (92, 93) which, in response to the internal refresh instruction signal, generates a refresh enable signal (.phi..sub.R) intermittently at a predetermined interval, a circuit (94, 95, 96, 98) which, in response to the refresh enable signal, refreshes data in the memory cells, and a circuit (99) which, in response to the internal refresh instruction signal and refresh enable signal, activates the substrate bias generator in the same cycle as the cycle of generation of the refresh enable signal and only for a time shorter than the cycle of generation of the refresh enable signal. The above construction contributes to a reduced power consumption in the dynamic random access memory.
摘要翻译：一种具有自刷新功能的动态随机存取存储器，其包括适于被间歇地驱动以向半导体衬底（15）施加偏置电位的衬底偏置发生器（100）。该存储装置包括用于响应于外部刷新指令信号产生内部刷新指令信号（phi S）的电路（91），响应于内部刷新指令信号产生刷新的电路（92,93）使能信号（phi R）以预定的间隔间歇地连接到响应于刷新使能信号刷新存储器单元中的数据的电路（94,95,96,98）和响应于电路（99）的电路（99）对于内部刷新指令信号和刷新使能信号，在与产生刷新使能信号的周期相同的周期中，仅在比生成刷新使能信号的周期短的时间内激活衬底偏置发生器。上述结构有助于动态随机存取存储器中的功耗降低。

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