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21. 发明申请

US20090179681A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090179681A1
公开(公告)日：2009-07-16
申请号：US12351426
申请日：2009-01-09
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： G06F1/04
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

22. 发明授权

US06878992B2 Vertical-type power MOSFET with a gate formed in a trench 有权
标题翻译：垂直型功率MOSFET，其栅极形成在沟槽中
公开(公告)号：US06878992B2
公开(公告)日：2005-04-12
申请号：US10091423
申请日：2002-03-07
申请人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
发明人： Yusuke Kawaguchi , Norio Yasuhara , Kazutoshi Nakamura , Akio Nakagawa , Syotaro Ono
IPC分类号： H01L21/28 , H01L21/336 , H01L29/41 , H01L29/423 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66666 , H01L29/42368 , H01L29/7828
摘要： A power MOSFET comprises, between source and drain electrodes, a low resistive semiconductor substrate of a first conductivity type, a drift layer of the first conductivity type formed on the semiconductor substrate, a high resistive epitaxial layer of the first conductivity type formed on the drift layer, trenches formed to extend from a surface of the epitaxial layer into the drift layer, gate electrodes buried in the trenches with gate insulating films interposed between the gate electrodes and walls of the trenches, low resistive source layers of the first conductivity type formed in a surface region of the epitaxial layer adjacent to the gate insulating films, and a base layer of a second conductivity type formed in the surface region of the epitaxial layer, wherein the epitaxial layer intervening between the trenches is depleted in a case where 0 volt is applied between the source electrode and the gate electrodes.
摘要翻译：功率MOSFET在源极和漏极之间包括第一导电类型的低电阻半导体衬底，形成在半导体衬底上的第一导电类型的漂移层，形成在漂移上的第一导电类型的高电阻外延层形成为从外延层的表面延伸到漂移层中的沟槽，埋入沟槽中的栅电极，栅极绝缘膜插入在栅电极和沟槽的壁之间，形成在第一导电类型的低电阻源层与栅极绝缘膜相邻的外延层的表面区域和形成在外延层的表面区域中的第二导电类型的基极层，其中在0伏特的情况下，介于沟槽之间的外延层被耗尽施加在源电极和栅电极之间。

23. 发明授权

US06614077B2 Semiconductor device improved in ESD reliability 有权
标题翻译：半导体器件提高了ESD可靠性
公开(公告)号：US06614077B2
公开(公告)日：2003-09-02
申请号：US09796427
申请日：2001-03-02
申请人： Kazutoshi Nakamura , Akio Nakagawa , Yusuke Kawaguchi
发明人： Kazutoshi Nakamura , Akio Nakagawa , Yusuke Kawaguchi
IPC分类号： H01L2362
CPC分类号： H01L29/7393 , H01L29/7394 , H01L29/749 , H01L2924/0002 , H01L2924/00
摘要： In an LDMOS, a p+-type anode layer is formed adjacent to an n+-type drain layer. The anode layer makes no contribution to an operation of the LDMOS at a rated voltage and generates holes at the time of ESD. The holes flow into the base layer through the active layer. Electrons flow from a source layer into the drain layer through the active layer. A parasitic thyristor of the LDMOS thus operates, with the result that a source-to-drain holding voltage can be lowered when a large current flows and the current distribution can be uniformed.
摘要翻译：在LDMOS中，与n +型漏极层相邻形成p +型阳极层。阳极层对额定电压下的LDMOS的操作没有贡献，并且在ESD时产生空穴。孔通过活性层流入基层。电子从源极层通过有源层流入漏极层。因此，LDMOS的寄生晶闸管因此工作，结果是当大电流流动并且电流分布可以均匀化时，源极到漏极保持电压可以降低。

24. 发明授权

US06297534B1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US06297534B1
公开(公告)日：2001-10-02
申请号：US09413811
申请日：1999-10-07
申请人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
发明人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L2976
CPC分类号： H01L29/7816 , H01L29/0634 , H01L29/1095 , H01L29/7824
摘要： A first conductivity type active layer having high resistance is provided on an insulation region. A second conductivity type base layer is selectively formed on a surface of the first conductivity type active layer. A first conductivity type source layer is selectively formed on a surface of the second conductivity type base layer. A first conductivity type drain layer is selectively formed on a surface of the first conductivity type active layer. A gate electrode is formed facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer. A plurality of first and second conductivity type semiconductor regions are formed between the second conductivity type base layer and the first conductivity type drain layer. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. Bottom portions of the second conductivity type semiconductor regions are shallower than the interface between the first conductivity type active layer and the insulation region. According to the present invention, low ON resistance and high withstand voltage are realized at the same time.
摘要翻译：在绝缘区域上设置具有高电阻的第一导电型有源层。在第一导电型有源层的表面上选择性地形成第二导电型基极层。第一导电型源极层选择性地形成在第二导电型基极层的表面上。第一导电型漏极层选择性地形成在第一导电型有源层的表面上。栅极电极通过栅极绝缘膜形成在第一导电型源极层和第一导电型有源层之间的第二导电型基极层的表面区域。在第二导电型基极层和第一导电型漏极层之间形成多个第一和第二导电型半导体区域。每个第二导电类型半导体区域与第一导电类型半导体区域中的每一个交替布置。漏极电流通过第一导电型半导体区域从第一导电型源极层流到第一导电型漏极层。第二导电类型半导体区域的底部比第一导电型有源层和绝缘区域之间的界面浅。根据本发明，同时实现低导通电阻和高耐受电压。

25. 发明授权

US07115946B2 MOS transistor having an offset region 有权
标题翻译： MOS晶体管具有偏移区域
公开(公告)号：US07115946B2
公开(公告)日：2006-10-03
申请号：US09956015
申请日：2001-09-20
申请人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
发明人： Yusuke Kawaguchi , Kazutoshi Nakamura , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/66681 , H01L27/088 , H01L29/0696 , H01L29/0847 , H01L29/42368 , H01L29/4238 , H01L29/66659 , H01L29/66674 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes a semiconductor region of a first conductivity type, a drain region of the first conductivity type, an offset region of the first conductivity type, a body region of the second conductivity type, a source region of the first conductivity type, a gate insulating film and a gate electrode. The drain region is provided in a surface of the semiconductor region and is shaped like a stripe. The offset region is provided in the surface of the semiconductor region and surrounds the drain region. The body region is provided in the surface of the semiconductor region and surrounds the offset region. The source region is provided in a surface of the body region and surrounds the offset region. The gate insulating film is provided on a part of the body region. The gate electrode is provided on the gate insulating film.
摘要翻译：半导体器件包括第一导电类型的半导体区域，第一导电类型的漏极区域，第一导电类型的偏移区域，第二导电类型的体区域，第一导电类型的源极区域，栅极绝缘膜和栅电极。漏极区域设置在半导体区域的表面中并且形状为条状。偏移区域设置在半导体区域的表面中并且围绕漏极区域。身体区域设置在半导体区域的表面中并且包围偏移区域。源区域设置在身体区域的表面中并且围绕偏移区域。栅极绝缘膜设置在身体区域的一部分上。栅电极设置在栅极绝缘膜上。

26. 发明申请

US20050056890A1 Offset-gate-type semiconductor device 失效
标题翻译：偏移栅型半导体器件
公开(公告)号：US20050056890A1
公开(公告)日：2005-03-17
申请号：US10957692
申请日：2004-10-05
申请人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
发明人： Norio Yasuhara , Syotaro Ono , Kazutoshi Nakamura , Yusuke Kawaguchi , Shinichi Hodama , Akio Nakagawa
IPC分类号： H01L21/265 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/76
CPC分类号： H01L29/402 , H01L21/26586 , H01L29/1045 , H01L29/1079 , H01L29/1083 , H01L29/41725 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/41775 , H01L29/456 , H01L29/66636 , H01L29/66659 , H01L29/78 , H01L29/7835
摘要： A semiconductor device includes a first semiconductor region having a first conductivity type, a second semiconductor region formed on the first semiconductor region and having the first conductivity type, a third semiconductor region formed in a surface of the second semiconductor region and having a second conductivity type, a fourth semiconductor region formed in the surface of the second semiconductor region and having the second conductivity type, and a gate structure formed on the second and fourth semiconductor region. The semiconductor device further includes a conductive member arranged in the trench extending from a surface of the fourth semiconductor region to the first semiconductor region, the trench having one sidewall surface flush with a sidewall surface of the gate structure.
摘要翻译：半导体器件包括具有第一导电类型的第一半导体区域，形成在第一半导体区域上并且具有第一导电类型的第二半导体区域，形成在第二半导体区域的表面中并具有第二导电类型的第三半导体区域形成在第二半导体区域的表面上并具有第二导电类型的第四半导体区域以及形成在第二和第四半导体区域上的栅极结构。半导体器件还包括布置在从第四半导体区域的表面延伸到第一半导体区域的沟槽中的导电构件，沟槽具有与栅极结构的侧壁表面齐平的一个侧壁表面。

27. 发明授权

US06864533B2 MOS field effect transistor with reduced on-resistance 有权
公开(公告)号：US06864533B2
公开(公告)日：2005-03-08
申请号：US09949646
申请日：2001-09-12
申请人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
发明人： Norio Yasuhara , Akio Nakagawa , Yusuke Kawaguchi , Kazutoshi Nakamura
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78 , H01L29/76
CPC分类号： H01L29/7816 , H01L29/0692 , H01L29/0696 , H01L29/0847 , H01L29/0878 , H01L29/0886 , H01L29/1045 , H01L29/4175 , H01L29/41766 , H01L29/7801 , H01L29/7818 , H01L29/7824 , H01L29/7833 , H01L29/7835
摘要： A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

28. 发明授权

US08497720B2 Semiconductor device 失效
公开(公告)号：US08497720B2
公开(公告)日：2013-07-30
申请号：US13527678
申请日：2012-06-20
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： H03K3/017
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

29. 发明授权

US08248128B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08248128B2
公开(公告)日：2012-08-21
申请号：US13110971
申请日：2011-05-19
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： H03K3/017
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.
摘要翻译：一种半导体器件包括：具有多级的第一延迟元件的电压控制型时钟产生电路，其振荡频率根据施加到第一延迟元件的控制电压而被控制; 具有串联连接的多级第二延迟元件的延迟电路; 以及选择电路，从由各个第二延迟元件的多级输出的脉冲信号中选择一个。第一延迟元件和第二延迟元件具有形成在同一半导体衬底上的相同结构，并且根据控制电压来调整第二延迟元件的延迟量。

30. 发明授权

US07973580B2 Semiconductor device 有权
公开(公告)号：US07973580B2
公开(公告)日：2011-07-05
申请号：US12986500
申请日：2011-01-07
申请人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
发明人： Kazutoshi Nakamura , Toru Takayama , Yuki Kamata , Akio Nakagawa , Yoshinobu Sano , Toshiyuki Naka
IPC分类号： H03K3/017
CPC分类号： H03K5/00006 , G06F1/08 , H02J1/00 , H02M3/156 , H03K2005/00293 , H03L7/0996 , Y10T307/50
摘要： A semiconductor device includes: a voltage-control-type clock generation circuit having a plurality of stages of first delay elements and whose oscillation frequency is controlled according to a control voltage applied to the first delay elements; a delay circuit having a plurality of stages of second delay elements connected serially; and a selection circuit selecting one from pulse signals output by the plurality of stages of respective second delay elements. The first delay elements and the second delay elements have a same structure formed on a same semiconductor substrate, and a delay amount of the second delay elements is adjusted according to the control voltage.

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