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21. 发明授权

US07012845B2 Nonvolatile memory with control circuit adapted to distinguish between command signal interface specifications and having an error correction function 有权
标题翻译：具有用于区分命令信号接口规范并具有纠错功能的控制电路的非易失性存储器
公开(公告)号：US07012845B2
公开(公告)日：2006-03-14
申请号：US11053423
申请日：2005-02-09
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G11C7/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

22. 发明申请

US20050141300A1 Nonvolatile memory 有权
标题翻译：非易失性存储器
公开(公告)号：US20050141300A1
公开(公告)日：2005-06-30
申请号：US11053423
申请日：2005-02-09
申请人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
发明人： Kenji Kozakai , Takeshi Nakamura , Tatsuya Ishii , Motoyasu Tsunoda , Shinya Iguchi , Junichi Maruyama
IPC分类号： G06F12/16 , G06F12/02 , G11C16/02 , G11C16/06 , G11C16/34 , G11C29/00 , G11C29/42 , G11C7/00
CPC分类号： G06F12/0246 , G06F11/1068 , G06F12/06 , G06F2212/1036 , G11C16/04 , G11C16/10 , G11C16/349 , G11C29/44 , G11C29/76 , G11C2029/0409
摘要： For a nonvolatile memory permitting electrical writing and erasing of information to be stored, such as a flash memory, the load on the system developer is to be reduced, and it is to be made possible to avoid, even if such important data for the system as management and address translation information are damaged, an abnormal state in which the system becomes unable to operate. The nonvolatile memory is provided with a replacing function to replace a group of memory cells including defective memory cells which are incapable of normal writing or erasion with a group of memory cells including no defective memory cell, a numbers of rewrites averaging function to grasp the number of data rewrites in each group of memory cells and to so perform replacement of memory cell groups that there may arise no substantial difference in the number of rewrites among a plurality of memory cell groups, and an error correcting function to detect and correct any error in data stored in the memory array, wherein first address translation information deriving from the replacing function and second address translation information deriving from the numbers of rewrites averaging function are stored in respectively prescribed areas in the memory array, and the first address translation information and second address translation information concerning the same memory cell group are stored in a plurality of sets in a time series.
摘要翻译：对于允许电子写入和擦除要存储的信息（例如闪存）的非易失性存储器，系统开发者的负载将被减少，并且即使这样的系统的重要数据也可以避免由于管理和地址转换信息被破坏，系统无法运行的异常状态。非易失性存储器设置有替换功能，以替换包括不能正常写入或擦除的缺陷存储器单元的存储器单元组，所述存储器单元不包括不存在缺陷存储器单元的存储单元组，重写次数用于掌握数量的每个存储器单元组中的数据重写，并且因此执行存储单元组的替换，使得多个存储单元组之间的重写次数可能没有显着差异，以及用于检测和校正任何错误的错误校正功能存储在存储器阵列中的数据，其中从替换功能导出的第一地址转换信息和从重写平均函数导出的第二地址转换信息被存储在存储器阵列中的分别规定的区域中，并且第一地址转换信息和第二地址关于相同存储单元组的翻译信息是sto 以时间序列的多个集合中的红色。

23. 发明授权

US06606347B1 Multistage interference canceller using primary and secondary path timings 有权
标题翻译：多级干扰消除器使用主路径和辅助路径时序
公开(公告)号：US06606347B1
公开(公告)日：2003-08-12
申请号：US09556406
申请日：2000-04-24
申请人： Tatsuya Ishii
发明人： Tatsuya Ishii
IPC分类号： H04B1707
CPC分类号： H04B1/71075
摘要： Each of path search unit 41 . . . 4N performs a path-searching on a received signal rin to output a primary path timing signal 8 indicating primary path timings. Each of IEUs 11 . . . 1N in a first stage performs a despreading or the like on the basis of the primary path timing signal 8 to generate a symbol replica signal 51 and a chip replica signal 6. Subtractor 31 subtracts the sum of chip replica signals 6 from the received signal rin to generate a residual signal 7. Each of path search units 41 . . . 4N performs a path-searching on the residual signal 7, and outputs a secondary path signal 9 indicating secondary path timings. A primary path timing of which SIR is low and which has a temporary secondary path timing which is near to the primary path timing is not selected as a secondary path timing but the corresponding temporary secondary path is selected as the secondary path timing. A primary path timing of which SIR is not low or which does not have a temporary secondary path timing which is near to the primary path timing is selected as a secondary path timing. Each of IEUs 11 . . . 1N in the second and the following stages performs a despreading or the like on the basis of the secondary path timing signal 9.
摘要翻译：路径搜索单元41中的每一个。。。 4N对接收到的信号rin执行路径搜索以输出指示主路径定时的主路径定时信号8。每个IEU 11。。。第一级中的1N在主路径定时信号8的基础上进行解扩等，生成符号复制信号51和芯片复制信号6.减法器31从接收信号rin中减去片复制信号6的和以产生残留信号7.每个路径搜索单元41。。。 4N对残差信号7进行路径搜索，并且输出指示次路径定时的次路径信号9。没有选择SIR为低并且具有接近主路径定时的临时次路径定时的主路径定时作为次路径定时，而是选择对应的临时辅助路径作为次路径定时。选择SIR不低或不具有接近主路径定时的临时次路径定时的主路径定时作为次路径定时。每个IEU 11。。。在第二和第二级中的1N根据次路径定时信号9进行解扩等。

24. 发明授权

US06452838B1 Nonvolatile memory system, semiconductor memory and writing method 有权
公开(公告)号：US06452838B1
公开(公告)日：2002-09-17
申请号：US09993685
申请日：2001-11-27
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0491 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/3404 , G11C16/3431 , G11C16/3459 , G11C2216/18
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

25. 发明授权

US06226212B1 Semiconductor memory device, nonvolatile semiconductor memory device, and their data reading method 失效
标题翻译：半导体存储器件，非易失性半导体存储器件及其数据读取方法
公开(公告)号：US06226212B1
公开(公告)日：2001-05-01
申请号：US09050885
申请日：1998-03-31
申请人： Yoshinori Sakamoto , Tatsuya Ishii , Atsushi Nozoe , Hitoshi Miwa , Kazuyoshi Oshima
发明人： Yoshinori Sakamoto , Tatsuya Ishii , Atsushi Nozoe , Hitoshi Miwa , Kazuyoshi Oshima
IPC分类号： G11C702
CPC分类号： G11C16/28 , G11C7/06 , G11C7/065 , G11C11/5621 , G11C11/5642 , G11C16/0416 , G11C29/00
摘要： In order to eliminate erroneous reading of data by preventing noise which might otherwise be transmitted at the data reading time through parasitic capacitance in the data lines to other data lines, switches (Qt1 and Qt1′) are interposed between a sense amplifier (SA) for amplifying the potential of a data line (DL) and the data line, and the sense amplifier is fed with an operating voltage after the potential of the data line is transmitted to the sense amplifier, and the switch is turned off.
摘要翻译：为了通过防止数据读取时通过数据线中的寄生电容发送到其他数据线的噪声来消除数据的错误读取，开关（Qt1和Qt1'）插入在用于放大数据线（DL）和数据线的电位，并且在数据线的电位被传送到读出放大器之后，感测放大器被馈送工作电压，并且开关被关断。

26. 发明授权

US6009016A Nonvolatile memory system semiconductor memory and writing method 有权
公开(公告)号：US6009016A
公开(公告)日：1999-12-28
申请号：US323684
申请日：1999-06-02
申请人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
发明人： Tatsuya Ishii , Hitoshi Miwa , Osamu Tsuchiya , Shooji Kubono
IPC分类号： G11C7/00 , G11C11/34 , G11C16/04 , G11C16/10
CPC分类号： G11C16/3427 , G11C16/10 , G11C16/3459
摘要： A nonvolatile semiconductor memory recovers variation in the threshold of a memory cell due to disturbance related to a word line. The nonvolatile memory continuously performs many writing operations without carrying out single-sector erasing after each writing operation, performing the additional writing operations quicker than the usual writing operation, and lightening the burden imposed on software for use in additional writing. The data stored in a designated sector is read out before being saved in a register, and the selected sector is subjected to single-sector erasing when a predetermined command is given. Then write expected value data is formed from the saved data and data to be additionally written, completing the writing operation.

27. 发明授权

US5389873A Pressure contact chip and wafer testing device 失效
标题翻译：压接芯片和晶圆测试装置
公开(公告)号：US5389873A
公开(公告)日：1995-02-14
申请号：US62538
申请日：1993-05-18
申请人： Tatsuya Ishii , Masatoshi Matsumoto
发明人： Tatsuya Ishii , Masatoshi Matsumoto
IPC分类号： G01R1/073 , G01R31/26 , H01L21/66 , G01R1/04
CPC分类号： G01R1/07314
摘要： In order to enable a burn-in test in a wafer state even if a semiconductor wafer has a number of bonding pads on every chip, bumps (15) are brought into contact with bonding pads (5c) of all chips (5b) provided on a semiconductor wafer (5), so that voltages are simultaneously applied to all chips. The bumps (15) are arranged on a translucent polyimidc film (10) in mirror image relation to the bonding pads (5c), so that the former are aligned with the latter with alignment marks (34a, 34b) through an opening (11a) and the polyimide film (10) with a light-optic microscope (13). A heater (14) is brought into dose contact with the back surface of the semiconductor wafer (5), to heat the same. Thus, potential defective chips can be screened before assembling steps, to reduce the cost. Failure analysis can be quickly performed with excellent maintenance on a process line, to improve the yield and the throughput.
摘要翻译：为了能够在晶片状态下进行老化试验，即使半导体晶片在每个芯片上具有多个接合焊盘，凸块（15）与设置在其上的所有芯片（5b）的焊盘（5c）接触半导体晶片（5），使得电压同时施加到所有芯片。凸起（15）与接合焊盘（5c）以镜像关系布置在半透明聚酰亚胺膜（10）上，使得前者通过开口（11a）与对准标记（34a，34b）与后者对准，和具有光学显微镜（13）的聚酰亚胺膜（10）。加热器（14）与半导体晶片（5）的背面进行剂量接触以加热。因此，可以在组装步骤之前屏蔽潜在的有缺陷的芯片，以降低成本。故障分析可以在生产线上进行良好的维护，从而提高产量和产量。

28. 发明授权

US5250831A DRAM device having a memory cell array of a divided bit line type 失效
标题翻译：具有分割位线型存储单元阵列的DRAM装置
公开(公告)号：US5250831A
公开(公告)日：1993-10-05
申请号：US673823
申请日：1991-03-22
申请人： Tatsuya Ishii
发明人： Tatsuya Ishii
IPC分类号： H01L27/10 , G11C11/4097 , H01L21/8242 , H01L23/528 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10835 , G11C11/4097 , H01L23/528 , H01L2924/0002 , Y10S257/908 , Y10S257/91 , Y10S257/911
摘要： A memory cell array (50) of a DRAM has a so-called divided bit line structure including two regions (50a and 50) divided from each other. One bit line (24) of a bit line pair is connected to a predetermined memory cell in a first memory cell array block (50a) and is kept in unloaded state in a second memory cell array block (50b). The other bit line (25) of a bit line pair is kept in unloaded state in the first memory cell array block (50a) and is connected to a predetermined memory cell in a first memory cell array block (50b). In these structures, the load state is kept same in both bit lines of the bit line pair. In the memory cell array, four memory cells are disposed in a cross-relationship, and are connected to the bit line (24) through a contact portion (17) used in common by the four memory cells. The word lines (20a and 20b) are formed to obliquely cross the bit lines and to extend perpendicularly to each other. Capacitors (3) in the memory cells have portions extended over the word lines. Transfer gate transistors (4) in the memory cells have source/drain regions (11 and 13) formed by means of self-alignment with respect to the word lines. Thus, controllability of channel lengths of the transfer gate transistors in the memory cells is improved.
摘要翻译： DRAM的存储单元阵列（50）具有包括彼此分开的两个区域（50a和50）的所谓的分割位线结构。位线对的一个位线（24）连接到第一存储单元阵列块（50a）中的预定存储单元，并在第二存储单元阵列块（50b）中保持在无载状态。位线对的另一位线（25）在第一存储单元阵列块（50a）中被保持为无载状态，并连接到第一存储单元阵列块（50b）中的预定存储单元。在这些结构中，负载状态在位线对的两个位线中保持相同。在存储单元阵列中，四个存储单元以交叉关系布置，并且通过四个存储单元共同使用的接触部分（17）连接到位线（24）。字线（20a和20b）形成为倾斜地跨越位线并且彼此垂直地延伸。存储器单元中的电容器（3）具有在字线上延伸的部分。存储单元中的传输栅晶体管（4）具有通过相对于字线的自对准形成的源/漏区（11和13）。因此，提高了存储单元中传输栅极晶体管的沟道长度的可控性。

29. 发明授权

US4970580A Semiconductor memory device having protruding cell configuration 失效
标题翻译：具有突出单元结构的半导体存储器件
公开(公告)号：US4970580A
公开(公告)日：1990-11-13
申请号：US269762
申请日：1988-11-10
申请人： Tatsuya Ishii
发明人： Tatsuya Ishii
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10841
摘要： A transistor (4, 5, 7, 11) is formed on a sidewall of a projection (22) which is formed on a major surface of a semiconductor substrate (1), and a capacitor (3, 5, 6) is formed on the surface of the semiconductor substrate (1) around the projection (22), to be connected to the transistor. At the forward end of the projection, an interconnection member (8) is connected to a source/drain region (11) of the transistor. Further, a transistor (4, 5, 7, 11)n is formed on an upper surface portion of a projection (22) which is formed on a major surface of a semiconductor substrate (1), and a capacitor (3, 5, 6) to be connected to the transistor is formed on a sidewall of the projection (22). An isolation oxide film (2) is formed on the major surface of the semiconductor substrate around the projection and under the capacitor. Further, a first projection (62) is formed on a major surface of a semiconductor substrate (1), and a second projection (22), which is smaller than the first projection (62), is formed on the first projection (62). A transistor (4, 5, 7, 11) is formed on a sidewall of the second projection (22) and a capacitor (3, 5, 6) is formed on a sidewall of the second projection (62) respectively, such that the transistor and the capacitor are connected with each other through an impurity layer (5) formed on an upper surface of the first projection (62).
摘要翻译：在形成在半导体衬底（1）的主表面上的突起（22）的侧壁上形成晶体管（4,5,7,11），并且电容器（3,5,6）形成在半导体衬底围绕投影（22）的半导体衬底（1）的表面，以连接到晶体管。在突起的前端，互连构件（8）连接到晶体管的源/漏区（11）。此外，晶体管（4,5,7,11）n形成在形成在半导体衬底（1）的主表面上的突起（22）的上表面部分上，并且电容器（3,5， 6）被形成在突起（22）的侧壁上。隔离氧化膜（2）形成在半导体衬底的主表面周围的突起和电容器下面。此外，在半导体基板（1）的主表面上形成有第一突起（62），并且在第一突起（62）上形成有小于第一突起（62）的第二突起（22）。在第二突起（22）的侧壁上形成晶体管（4,5,7,11），并且电容器（3,5,6）分别形成在第二突起（62）的侧壁上，使得晶体管和电容器通过形成在第一突起（62）的上表面上的杂质层（5）相互连接。

30. 发明授权

US4849279A Insect-repellent assembly 失效
标题翻译：防虫装配
公开(公告)号：US4849279A
公开(公告)日：1989-07-18
申请号：US159535
申请日：1988-02-12
申请人： Takashi Toyama , Haruyoshi Narita , Tatsuya Ishii
发明人： Takashi Toyama , Haruyoshi Narita , Tatsuya Ishii
IPC分类号： A01N25/18
CPC分类号： A01N25/18 , Y10S428/905 , Y10T428/30 , Y10T442/2541
摘要： An insect-repellent assembly comprising a carrier member containing activated carbon fibers and an insect-repellent agent contained in said carrier member. Cockroach-repellent agents are preferable as the insect-repellent agent. The insect-repellent assembly of the present invention maintains its insect-repellent effect for a extended period of time.

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