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21. 发明授权

US08680872B2 Identification of false positives in high impedance fault detection 失效
标题翻译：识别高阻抗故障检测中的假阳性
公开(公告)号：US08680872B2
公开(公告)日：2014-03-25
申请号：US12569294
申请日：2009-09-29
申请人： Tomasz J. Nowicki , Grzegorz M. Swirszcz
发明人： Tomasz J. Nowicki , Grzegorz M. Swirszcz
IPC分类号： G01R31/02
CPC分类号： G01R31/085 , G01R31/086 , G01R31/088 , Y04S10/522
摘要： A method, system and computer program product are disclosed for identifying false positive indications of high impedance faults in an AC electric power transmission and distribution network. In one embodiment, the method comprises using a procedure to monitor a phase conductor of the network for faults, said procedure generating a fault signal indicating a specified fault in the conductor. In this embodiment, the voltage and current waveform of the electric power conducted through the conductor are monitored. When a phase shift in said waveform is detected over a defined period of time, and said detected phase shift meets one or more given criteria, a correction signal is generated indicating that said fault signal is a false indication of the specified fault. The given criteria may include, for example, that the phase shift is more than a threshold value for a specified period of time.
摘要翻译：公开了一种用于识别交流电力输配电网络中高阻抗故障的假阳性指示的方法，系统和计算机程序产品。在一个实施例中，该方法包括使用用于监视网络的相导体以用于故障的过程，所述过程产生指示导体中指定故障的故障信号。在本实施例中，监视通过导体传导的电力的电压和电流波形。当在规定的时间段内检测到所述波形中的相移，并且所述检测到的相移符合一个或多个给定标准时，产生指示所述故障信号是指定故障的错误指示的校正信号。给定的标准可以包括例如相移在特定时间段内大于阈值。

22. 发明申请

US20120330450A1 COMPREHENSIVE ANALYSIS OF QUEUE TIMES IN MICROELECTRONIC MANUFACTURING 有权
标题翻译：微电子制造中队列时间的综合分析
公开(公告)号：US20120330450A1
公开(公告)日：2012-12-27
申请号：US13604986
申请日：2012-09-06
申请人： Robert J. Baseman , Tomasz J. Nowicki
发明人： Robert J. Baseman , Tomasz J. Nowicki
IPC分类号： G06F17/50
CPC分类号： G06N99/005 , G06F2217/10
摘要： A system for determining a group of semiconductor manufacturing process steps with a similar influence on individual semiconductor products. The system generates a first table including time stamps for the individual semiconductor products. The system creates a second table including Q-times based on the first table. The Q-times refers to time differences between every pair of the time stamps. The system forms a dependency table by grouping the Q-times with similar dependencies together. The system identifies groups of the similar dependencies. The system extracts semiconductor process steps belonging to the groups.
摘要翻译：一种用于确定对各个半导体产品具有相似影响的一组半导体制造工艺步骤的系统。该系统产生包括各个半导体产品的时间戳的第一表。系统创建第二个表，其中包括基于第一个表的Q次。 Q时间是指每对时间戳之间的时差。系统通过将Q次与相似的依赖关系分组在一起来形成依赖关系表。系统识别类似依赖关系的组。系统提取属于这些组的半导体工艺步骤。

23. 发明申请

US20110284029A1 FOREIGN MATERIAL CONTAMINATION DETECTION 有权
标题翻译：外来物质污染检测
公开(公告)号：US20110284029A1
公开(公告)日：2011-11-24
申请号：US12783702
申请日：2010-05-20
申请人： Robert J. Baseman , Tomasz J. Nowicki
发明人： Robert J. Baseman , Tomasz J. Nowicki
IPC分类号： B08B7/04
CPC分类号： B08B13/00 , H01L21/67288 , Y10T436/11
摘要： There are provided a system, method and computer program product for detecting foreign materials in a semiconductor manufacturing process. The manufacturing process uses a plurality of semiconductor manufacturing tools. The system categorizes at least one monitoring wafer according to one or more categories. The system supplies the categorized monitoring wafer to a semiconductor manufacturing tool. The system observes a level of contamination on the categorized monitoring wafer. The system compares the level of contamination to a threshold. The system cleans the tool in a response to determining that the level of contamination is larger than the threshold. The system determines which category of the wafer leaves a highest level of contamination on the tool. The system identifies a root cause of the highest level of contamination on the tool.
摘要翻译：提供了一种用于在半导体制造工艺中检测异物的系统，方法和计算机程序产品。制造工艺使用多个半导体制造工具。该系统根据一个或多个类别对至少一个监视晶片进行分类。该系统将分类的监控晶片提供给半导体制造工具。该系统观察到分类监控晶片的污染程度。系统将污染水平与阈值进行比较。系统在响应中清洁工具以确定污染物的水平大于阈值。该系统确定哪个类别的晶片在工具上留下最高的污染水平。系统识别工具上最高污染水平的根本原因。

24. 发明授权

US08041571B2 Application of speech and speaker recognition tools to fault detection in electrical circuits 失效
标题翻译：语音和扬声器识别工具在电路故障检测中的应用
公开(公告)号：US08041571B2
公开(公告)日：2011-10-18
申请号：US11620173
申请日：2007-01-05
申请人： Sarah C. McAllister , Tomasz J. Nowicki , Jason W. Pelecanos , Grzegorz M. Swirszcz
发明人： Sarah C. McAllister , Tomasz J. Nowicki , Jason W. Pelecanos , Grzegorz M. Swirszcz
IPC分类号： G10L11/00 , G10L15/16 , H02H3/00
CPC分类号： G10L15/26
摘要： A method and apparatus detect and localize electric faults in electrical power grids and circuit. High impedance faults are detected by analyzing data from remote sensor units deployed over the network using the algorithms of speech and speaker analysis software. This is accomplished by converting the voltage and/or current waveform readouts from the sensors into a digital form which is then transmitted to a computer located either near the sensors or at an operations center. The digitized data is converted by a dedicated software or software/hardware interface to a format accepted by a reliable and stable software solution, such as speech or speaker recognition software. The speech or speaker recognition software must be “trained” to recognize various signal patterns that either indicate or not the occurrence of a fault. The readout of the speech or speaker recognition software, if indicating a fault, is transmitted to a central processor and displayed to provide information on the most likely type of fault. Automatic or human decision is then implemented based on the generated information.
摘要翻译：一种方法和装置，检测和定位电力电网和电路中的电气故障。通过使用语音和扬声器分析软件的算法分析通过网络部署的远程传感器单元的数据来检测高阻抗故障。这是通过将来自传感器的电压和/或电流波形转换成数字形式来完成的，然后将其传输到位于传感器附近或操作中心的计算机。数字化数据由专用软件或软件/硬件接口转换为由可靠和稳定的软件解决方案接受的格式，如语音或扬声器识别软件。语音或扬声器识别软件必须经过“训练”以识别指示或不发生故障的各种信号模式。语音或扬声器识别软件的读出（如果指示故障）被发送到中央处理器并显示以提供关于最可能类型的故障的信息。然后基于生成的信息实现自动或人为决定。

25. 发明申请

US20080155484A1 SYSTEM AND METHOD FOR MEMORY ELEMENT CHARACTERIZATION 审中-公开
标题翻译：用于记忆元素表征的系统和方法
公开(公告)号：US20080155484A1
公开(公告)日：2008-06-26
申请号：US12034811
申请日：2008-02-21
申请人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
发明人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
摘要翻译：用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。在存储元件的状态空间中计算安全区域，其表示稳定状态。执行瞬态分析以确定到达安全区域之一所需的路径和时间。基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

26. 发明授权

US07350170B2 System and method for memory element characterization 有权
标题翻译：用于记忆元素表征的系统和方法
公开(公告)号：US07350170B2
公开(公告)日：2008-03-25
申请号：US11142709
申请日：2005-06-01
申请人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
发明人： Bhavna Agrawal , Peter Feldmann , Sani R. Nassif , Tomasz J. Nowicki , Grzegorz Michal Swirszcz
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5031
摘要： A system and method for analyzing a memory element includes modeling the memory element using a simulation method and determining component response characteristics for components of the memory element. Safety regions are computed in a state space of the memory element, which indicate stable states. A transient analysis is performed to determine a path and time needed to reach one of the safety regions. Based on the path and time needed to reach one of the safety regions, a clock waveform or waveforms are determined which place a corresponding state in that safety region.
摘要翻译：用于分析存储元件的系统和方法包括使用模拟方法对存储器元件进行建模并确定存储元件的组件的组件响应特性。在存储元件的状态空间中计算安全区域，其表示稳定状态。执行瞬态分析以确定到达安全区域之一所需的路径和时间。基于到达安全区域之一所需的路径和时间，确定在该安全区域中放置相应状态的时钟波形或波形。

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