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21. 发明申请

US20110309334A1 Graphene/Nanostructure FET with Self-Aligned Contact and Gate 有权
标题翻译：具有自对准接触和栅极的石墨烯/纳米结构FET
公开(公告)号：US20110309334A1
公开(公告)日：2011-12-22
申请号：US12820341
申请日：2010-06-22
申请人： Josephine Chang , Isaac Lauer , Jeffrey Sleight
发明人： Josephine Chang , Isaac Lauer , Jeffrey Sleight
IPC分类号： H01L29/78 , H01L29/76 , H01L21/84
CPC分类号： H01L29/66628 , B82Y10/00 , H01L21/76897 , H01L29/0665 , H01L29/0669 , H01L29/1606 , H01L29/66742 , H01L29/778 , H01L29/78684 , H01L51/0048 , H01L51/0508
摘要： A method for forming a field effect transistor (FET) includes depositing a channel material on a substrate, the channel material comprising one of graphene or a nanostructure; forming a gate over a first portion of the channel material; forming spacers adjacent to the gate; depositing a contact material over the channel material, gate, and spacers; depositing a dielectric material over the contact material; removing a portion of the dielectric material and a portion of the contact material to expose the top of the gate; recessing the contact material; removing the dielectric material; and patterning the contact material to form a self-aligned contact for the FET, the self-aligned contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.
摘要翻译：一种用于形成场效应晶体管（FET）的方法，包括在衬底上沉积沟道材料，所述沟道材料包括石墨烯或纳米结构之一; 在所述通道材料的第一部分上形成栅极; 形成邻近门的间隔物; 在沟道材料，栅极和间隔物上沉积接触材料; 在所述接触材料上沉积介电材料; 去除介电材料的一部分和接触材料的一部分以暴露栅极的顶部; 使接触材料凹陷; 去除介电材料; 以及图案化所述接触材料以形成所述FET的自对准接触，所述自对准接触位于所述FET的源极区域和漏极区域之上，所述源极区域和所述漏极区域包括所述沟道材料的第二部分。

22. 发明授权

US07985633B2 Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors 有权
标题翻译：嵌入式DRAM集成电路，具有极薄的绝缘体上硅传导晶体管
公开(公告)号：US07985633B2
公开(公告)日：2011-07-26
申请号：US11929943
申请日：2007-10-30
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L21/84
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译：提供具有组合的存储器和逻辑功能的集成电路。一方面，提供集成电路。集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

23. 发明申请

US20100295021A1 Single Gate Inverter Nanowire Mesh 有权
标题翻译：单门逆变器纳米线网
公开(公告)号：US20100295021A1
公开(公告)日：2010-11-25
申请号：US12470128
申请日：2009-05-21
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L29/15 , H01L21/336 , H01L27/12
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供基于纳米线的设备。一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

24. 发明授权

US06806203B2 Method of forming a dual damascene structure using an amorphous silicon hard mask 失效
标题翻译：使用非晶硅硬掩模形成双镶嵌结构的方法
公开(公告)号：US06806203B2
公开(公告)日：2004-10-19
申请号：US10101540
申请日：2002-03-18
申请人： Timothy Weidman , Nikolaos Bekiaris , Josephine Chang , Phong H. Nguyen
发明人： Timothy Weidman , Nikolaos Bekiaris , Josephine Chang , Phong H. Nguyen
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76811 , H01L21/76813 , H01L21/76829
摘要： A method of forming a dual damascene structure on a substrate having a dielectric layer already formed thereon. In one embodiment the method includes depositing a first hard mask layer over the dielectric layer and depositing a second hard mask layer on the first hard mask layer, where the second hard mask layer is an amorphous silicon layer. Afterwards, formation of the dual damascene structure is completed by etching a metal wiring pattern and a via pattern in the dielectric layer and filling the etched metal wiring pattern and via pattern with a conductive material.
摘要翻译：在其上已经形成有电介质层的基板上形成双镶嵌结构的方法。在一个实施例中，该方法包括在电介质层上沉积第一硬掩模层并在第一硬掩模层上沉积第二硬掩模层，其中第二硬掩模层是非晶硅层。然后，通过在电介质层中蚀刻金属布线图案和通孔图案并用导电材料填充蚀刻的金属布线图案和通孔图案来完成双镶嵌结构的形成。

25. 发明授权

US08586455B1 Preventing shorting of adjacent devices 失效
标题翻译：防止相邻设备短路
公开(公告)号：US08586455B1
公开(公告)日：2013-11-19
申请号：US13471487
申请日：2012-05-15
申请人： Josephine Chang , Michael A. Guillorn , Balasubramanian Pranatharthiharan , Jeffrey William Sleight
发明人： Josephine Chang , Michael A. Guillorn , Balasubramanian Pranatharthiharan , Jeffrey William Sleight
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/76202 , H01L21/823431 , H01L21/845 , H01L27/1104 , H01L27/1108
摘要： Embodiments of the present invention provide a method of preventing electrical shorting of adjacent semiconductor devices. The method includes forming a plurality of fins of a plurality of field-effect-transistors on a substrate; forming at least one barrier structure between a first and a second fin of the plurality of fins; and growing an epitaxial film from the plurality of fins, the epitaxial film extending horizontally from sidewalls of at least the first and second fins and reaching the barrier structure situating between the first and second fins.
摘要翻译：本发明的实施例提供一种防止相邻半导体器件的电短路的方法。该方法包括在衬底上形成多个场效应晶体管的多个散热片; 在所述多个翅片的第一和第二翅片之间形成至少一个阻挡结构; 以及从所述多个翅片生长外延膜，所述外延膜从至少所述第一和第二鳍片的侧壁水平延伸并到达位于所述第一和第二鳍片之间的所述阻挡结构。

26. 发明授权

US08216902B2 Nanomesh SRAM cell 有权
标题翻译： Nanomesh SRAM单元
公开(公告)号：US08216902B2
公开(公告)日：2012-07-10
申请号：US12536741
申请日：2009-08-06
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L21/8234
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译：提供基于纳米线的设备。在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

27. 发明授权

US08084308B2 Single gate inverter nanowire mesh 有权
标题翻译：单门逆变器纳米线网
公开(公告)号：US08084308B2
公开(公告)日：2011-12-27
申请号：US12470128
申请日：2009-05-21
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L21/00 , H01L21/84 , H01L27/148 , H01L27/105
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a field-effect transistor (FET) inverter is provided. The FET inverter includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供基于纳米线的设备。一方面，提供了场效应晶体管（FET）逆变器。 FET反相器包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道，其中一个或多个更多的器件层掺杂有n型掺杂剂，并且器件层中的一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

28. 发明申请

US20110233634A1 Embedded DRAM Integrated Circuits with Extremely Thin Silicon-On-Insulator Pass Transistors 有权
标题翻译：嵌入式DRAM集成电路与极薄的绝缘体上硅晶体管
公开(公告)号：US20110233634A1
公开(公告)日：2011-09-29
申请号：US13153806
申请日：2011-06-06
申请人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
发明人： Jin Cai , Josephine Chang , Leland Chang , Brian L. Ji , Steven John Koester , Amlan Majumdar
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/10894
摘要： Integrated circuits having combined memory and logic functions are provided. In one aspect, an integrated circuit is provided. The integrated circuit comprises: a substrate comprising a silicon layer over a BOX layer, wherein a select region of the silicon layer has a thickness of between about three nanometers and about 20 nanometers; at least one eDRAM cell comprising: at least one pass transistor having a pass transistor source region, a pass transistor drain region and a pass transistor channel region formed in the select region of the silicon layer; and a capacitor electrically connected to the pass transistor.
摘要翻译：提供具有组合的存储器和逻辑功能的集成电路。一方面，提供集成电路。集成电路包括：衬底，其包括在BOX层上的硅层，其中硅层的选择区域具有在约3纳米和约20纳米之间的厚度; 至少一个eDRAM单元包括：至少一个传输晶体管，其具有形成在所述硅层的所述选择区域中的传输晶体管源极区域，传输晶体管漏极区域和传输晶体管沟道区域; 以及电连接到传输晶体管的电容器。

29. 发明申请

US20110031473A1 Nanomesh SRAM Cell 有权
标题翻译： Nanomesh SRAM单元
公开(公告)号：US20110031473A1
公开(公告)日：2011-02-10
申请号：US12536741
申请日：2009-08-06
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L27/11 , H01L29/66 , H01L21/8239
CPC分类号： H01L27/1203 , B82Y10/00 , H01L21/84 , H01L27/0688 , H01L27/11 , H01L27/1104 , Y10S977/938
摘要： Nanowire-based devices are provided. In one aspect, a SRAM cell includes at least one pair of pass gates and at least one pair of inverters formed adjacent to one another on a wafer. Each pass gate includes one or more device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the pass gate device layers surrounding the nanowire channels. Each inverter includes a plurality of device layers each having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region and a gate common to each of the inverter device layers surrounding the nanowire channels.
摘要翻译：提供基于纳米线的设备。在一个方面，SRAM单元包括在晶片上彼此相邻形成的至少一对通孔和至少一对反相器。每个通路门包括一个或多个器件层，每个器件层具有源区域，漏极区域和连接源区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个通过栅极器件层公共的栅极。每个反相器包括多个器件层，每个器件层具有源区域，漏极区域和连接源极区域和漏极区域的多个纳米线通道以及围绕纳米线通道的每个反相器器件层公共的栅极。

30. 发明授权

US06304844B1 Spelling speech recognition apparatus and method for communications 失效
标题翻译：拼写语音识别装置和通信方法
公开(公告)号：US06304844B1
公开(公告)日：2001-10-16
申请号：US09538657
申请日：2000-03-30
申请人： James Pan , Yoon Kim , Josephine Chang , Juinn-Yan Chen
发明人： James Pan , Yoon Kim , Josephine Chang , Juinn-Yan Chen
IPC分类号： G10L1502
CPC分类号： G10L15/187 , G10L15/02 , G10L2015/086
摘要： An accurate speech recognition system capable of rapidly processing greater varieties of words and operable in many different devices, but without the computational power and memory requirements, high power consumption, complex operating system, high costs, and weight of traditional systems. The utilization of individual letter utterances to transmit words allows voice information transfer for both person-to-person and person-to-machine communication for mobile phones, PDAs, and other communication devices. This invention is an apparatus and method for a speech recognition system comprising a microphone, front-end signal processor for generating parametric representations of speech input signals, a pronunciation database, a letter similarity comparator for comparing the parametric representation of the input signals with the parametric representations of letter pronunciations, and generating a sequence of associations between the input speech and the letters in the pronunciation database, a vocabulary database, a word similarity comparator for comparing an aggregated plurality of the letters with the words in the vocabulary database and generating a sequence of associations between them, and a display for displaying the selected letters and words for confirmation.
摘要翻译：一种精确的语音识别系统，能够快速处理更多种类的词语，并可在许多不同的设备中运行，但无需计算能力和内存要求，高功耗，复杂的操作系统，高成本和传统系统的重量。使用单个字母的话语来传输话语，可以为移动电话，PDA和其他通信设备的个人对个人和个人到机器的通信进行语音信息传输。本发明是一种用于语音识别系统的装置和方法，其包括麦克风，用于产生语音输入信号的参数表示的前端信号处理器，发音数据库，字母相似性比较器，用于将输入信号的参数表示与参数字母发音的表示，以及在发音数据库中产生输入语音和字母之间的关联序列，词汇数据库，词汇相似性比较器，用于将汇总的多个字母与词汇数据库中的单词进行比较，并产生序列它们之间的关联，以及用于显示所选择的字母和单词以进行确认的显示。

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