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21. 发明授权

US06861688B2 Line configuration for bit lines for contact-connecting at least one memory cell, semiconductor component with a line configuration and method for fabricating a line configuration 有权
标题翻译：用于连接至少一个存储单元的位线的线路配置，具有线路配置的半导体部件和用于制造线路配置的方法
公开(公告)号：US06861688B2
公开(公告)日：2005-03-01
申请号：US10288387
申请日：2002-11-05
申请人： Dirk Manger , Till Schlösser
发明人： Dirk Manger , Till Schlösser
IPC分类号： H01L21/4763 , H01L21/768 , H01L21/8242 , H01L27/108 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/10885
摘要： A bit line configuration for contact-connecting at least one memory cell, in particular a DRAM memory cell, has bit lines disposed above the plane of the memory cell. A first bit line in a first bit line level is disposed below a second bit line in a second bit line level and the second bit line penetrates through the first bit line at at least one location of the first bit line for the purpose of producing a contact with the at least one memory cell at penetration locations. It is thus possible to provide space-saving structures, in particular sub-8F2 structures.
摘要翻译：用于接触连接至少一个存储器单元，特别是DRAM存储单元的位线配置具有位于存储单元的平面之上的位线。第一位线电平中的第一位线设置在第二位线电平中的第二位线下方，并且第二位线在第一位线的至少一个位置处穿过第一位线，以产生第在穿透位置处与至少一个存储单元接触。因此，可以提供节省空间的结构，特别是8F 2结构。

22. 发明授权

US06798000B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US06798000B2
公开(公告)日：2004-09-28
申请号：US10275337
申请日：2002-12-18
申请人： Richard Johannes Luyken , Till Schlösser , Thomas Peter Haneder , Wolfgang Hönlein , Franz Kreupl
发明人： Richard Johannes Luyken , Till Schlösser , Thomas Peter Haneder , Wolfgang Hönlein , Franz Kreupl
IPC分类号： H01L2976
CPC分类号： H01L51/0595 , B82Y10/00 , G11C2213/17 , H01L51/0048 , H01L51/0508 , Y10S977/938
摘要： A field-effect transistor that having a nanowire, which forms a source region, a channel region and a drain region of the field-effect transistor, the nanowire being a semiconducting and/or metallically conductive nanowire. The field-effect transistor also has at least one nanotube, which forms a gate region of the field-effect transistor, the nanotube being a semiconducting and/or metallically conductive nanotube. The nanowire and the nanotube are arranged at a distance from one another or set up in such a manner that it is substantially impossible for there to be a tunneling current between the nanowire and the nanotube, and that the conductivity of the channel region of the nanowire can be controlled by means of a field effect as a result of an electric voltage being applied to the nanotube.
摘要翻译：具有纳米线的场效应晶体管，其形成场效应晶体管的源极区，沟道区和漏极区，纳米线是半导体和/或金属导电的纳米线。场效应晶体管还具有形成场效应晶体管的栅极区域的至少一个纳米管，纳米管是半导体和/或金属导电的纳米管。纳米线和纳米管彼此间隔一定距离或以这样的方式设置，使得在纳米线和纳米管之间基本上不可能存在隧穿电流，并且纳米线的沟道区的导电性可以通过施加到纳米管的电压的结果通过场效应来控制。

23. 发明授权

US06737689B1 FEMFET device and method for producing same 失效
标题翻译： FEMFET器件及其制造方法
公开(公告)号：US06737689B1
公开(公告)日：2004-05-18
申请号：US09857262
申请日：2001-07-16
申请人： Till Schlösser , Thomas Haneder
发明人： Till Schlösser , Thomas Haneder
IPC分类号： H01L2976
CPC分类号： H01L21/28291 , H01L28/56 , H01L29/516
摘要： The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.
摘要翻译：本发明涉及具有半导体衬底和设置在半导体衬底中的至少一个场效应晶体管的FEMFET器件。场效应晶体管具有源极区域，漏极区域，沟道区域和栅极堆叠。栅极堆叠具有至少一个铁电层，并且至少一个薄扩散阻挡层被布置在最低铁电层和半导体衬底之间，并且被配置为使得铁电层的组分向半导体内扩散基本上被防止。

24. 发明授权

US06538273B2 Ferroelectric transistor and method for fabricating it 有权
标题翻译：铁电晶体管及其制造方法
公开(公告)号：US06538273B2
公开(公告)日：2003-03-25
申请号：US09849910
申请日：2001-05-04
申请人： Josef Willer , Georg Braun , Till Schlösser , Thomas Haneder
发明人： Josef Willer , Georg Braun , Till Schlösser , Thomas Haneder
IPC分类号： H01L2902
CPC分类号： H01L29/78391
摘要： A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.
摘要翻译：公开了具有两个源极/漏极区域和设置在半导体衬底之间的沟道区域的铁电晶体管。金属中间层设置在沟道区域的表面上，并与半导体衬底形成肖特基二极管，并且在其表面上设置铁电层和栅电极。铁电晶体管使用与硅工艺技术相关的步骤制造。

25. 发明授权

US06504200B2 DRAM cell configuration and fabrication method 有权
公开(公告)号：US06504200B2
公开(公告)日：2003-01-07
申请号：US09951243
申请日：2001-09-12
申请人： Till Schlösser , Bernhard Sell , Josef Willer
发明人： Till Schlösser , Bernhard Sell , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L27/10876 , H01L27/10808 , H01L27/10823
摘要： Bit lines are arranged in the lower parts of trenches of a substrate. Word lines are located above the substrate except for protuberances or bulges, which extend downwards into the trenches and which are arranged above the bit lines. The transistors are vertical transistors whose source/drain regions are located below the word lines and between adjacent trenches. The capacitors are linked with the upper source/drain regions. Conductive structures that surround the word lines from the top and the sides while being insulated from the word lines and bordering on the upper source/drain regions can link the upper source/drain regions with the capacitors.

26. 发明授权

US06438022B2 Memory cell configuration 失效
标题翻译：内存单元配置
公开(公告)号：US06438022B2
公开(公告)日：2002-08-20
申请号：US09854259
申请日：2001-05-10
申请人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
发明人： Till Schlösser , Wolfgang Krautschneider , Franz Hofmann , Thomas-Peter Haneder
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： The memory cells of a memory cell configuration each have a selection transistor, a memory transistor and a ferroelectric capacitor. The selection transistor and the memory transistor are connected in series. The ferroelectric capacitor is connected between a control electrode of the memory transistor and a first terminal of the selection transistor.
摘要翻译：存储单元结构的存储单元分别具有选择晶体管，存储晶体管和铁电电容器。选择晶体管和存储晶体管串联连接。铁电电容器连接在存储晶体管的控制电极和选择晶体管的第一端子之间。

27. 发明授权

US06399433B2 Method for fabricating a memory cell 有权
标题翻译：用于制造存储单元的方法
公开(公告)号：US06399433B2
公开(公告)日：2002-06-04
申请号：US09773218
申请日：2001-01-31
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/55
摘要： A method for producing a storage cell includes forming a polycrystalline silicon layer on a semiconductor body having at least one selection transistor disposed in a first plane. An interspace is formed between two adjacent structures of the layer and one of the adjacent structures of the layer is placed on a surface of a first silicon plug. A cell plate electrode is formed in the interspace and a trench is formed in the layer. The trench reaches as far as the first plug surface and is filled with an insulating layer. The-layer is removed. A storage capacitor having a high-epsilon or ferroelectric dielectric and a storage node electrode is formed. The capacitor is disposed in a second plane in and above the body. The insulating layer is replaced with silicon to form a second silicon plug directly connected to the first plug. The second plug is electrically connected to the storage node electrode, and the first plane is electrically connected to the second plane through the first and second plugs.
摘要翻译：一种存储单元的制造方法包括在半导体本体上形成多晶硅层，该多晶硅层具有设置在第一平面中的至少一个选择晶体管。在层的两个相邻结构之间形成间隙，并且该层的相邻结构之一被放置在第一硅插头的表面上。在该间隙中形成单元板电极，并在该层中形成沟槽。沟槽达到第一插头表面的最远处，并且填充有绝缘层。该层被删除。形成具有高ε或铁电介质的存储电容器和存储节点电极。电容器设置在身体内和上方的第二平面内。绝缘层被硅替代以形成直接连接到第一插头的第二硅插头。第二插头电连接到存储节点电极，第一平面通过第一和第二插头电连接到第二平面。

28. 发明授权

US06229169B1 Memory cell configuration, method for fabricating it and methods for operating it 失效
标题翻译：存储单元配置，其制造方法及其操作方法
公开(公告)号：US06229169B1
公开(公告)日：2001-05-08
申请号：US09213724
申请日：1998-12-17
申请人： Franz Hofmann , Wolfgang Krautschneider , Wolfgang Rösner , Lothar Risch , Till Schlösser , Paul-Werner Basse
发明人： Franz Hofmann , Wolfgang Krautschneider , Wolfgang Rösner , Lothar Risch , Till Schlösser , Paul-Werner Basse
IPC分类号： H01L27108
CPC分类号： H01L27/11502 , H01L27/108 , H01L27/10823 , H01L27/10876 , H01L27/115 , H01L27/11507
摘要： A memory cell configuration contains a multiplicity of memory cells in a semiconductor substrate. Each of the memory cells has a selection transistor connected between a bit line and a storage element. The memory cells can each be driven via a first word line and a second word line, the first word line and the second word line crossing one another. The memory cell configuration is, in particular, a DRAM configuration.
摘要翻译：存储单元配置在半导体衬底中包含多个存储单元。每个存储单元具有连接在位线和存储元件之间的选择晶体管。每个存储器单元可以通过第一字线和第二字线驱动，第一字线和第二字线彼此交叉。存储单元配置尤其是DRAM配置。

29. 发明授权

US07595262B2 Manufacturing method for an integrated semiconductor structure 有权
标题翻译：集成半导体结构的制造方法
公开(公告)号：US07595262B2
公开(公告)日：2009-09-29
申请号：US11588591
申请日：2006-10-27
申请人： Till Schlösser
发明人： Till Schlösser
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/8236 , H01L21/8234 , H01L21/8242 , H01L21/336 , H01L21/44 , H01L21/28
CPC分类号： H01L27/10894 , H01L27/10882 , H01L27/10891
摘要： A manufacturing method for an integrated semiconductor structure and a corresponding semiconductor structure is disclosed. The method includes forming a peripheral circuitry in a peripheral device region, wherein the peripheral circuitry includes a peripheral transistor at least partially formed in the semiconductor substrate and having a first gate dielectric formed in a first high temperature process step. The method further includes forming a plurality of memory cells in a memory cell region, each of said memory cells including an access transistor at least partially formed in a semiconductor substrate and having a second gate dielectric formed in a second high temperature process step and having a metallic gate conductor. The first and second high temperature process steps are performed before a step of forming the metallic gate conductor.
摘要翻译：公开了一种用于集成半导体结构和相应的半导体结构的制造方法。该方法包括在外围设备区域中形成外围电路，其中外围电路包括至少部分地形成在半导体衬底中并具有在第一高温工艺步骤中形成的第一栅极电介质的外围晶体管。该方法还包括在存储器单元区域中形成多个存储单元，每个存储单元包括至少部分地形成在半导体衬底中并具有在第二高温工艺步骤中形成的第二栅电介质的存取晶体管，金属栅极导体。第一和第二高温工艺步骤在形成金属栅极导体的步骤之前进行。

30. 发明授权

US07030434B1 Arrangement with image sensors 有权
标题翻译：图像传感器布置
公开(公告)号：US07030434B1
公开(公告)日：2006-04-18
申请号：US10089570
申请日：2000-09-28
申请人： Wolfgang Krautschneider , Heribert Geib , Franz Hofmann , Till Schlösser
发明人： Wolfgang Krautschneider , Heribert Geib , Franz Hofmann , Till Schlösser
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14609
摘要： A memory transistor and a selection transistor of an image sensor are connected in series and between a bit line (B5) and a reference line (R5). A gate electrode of the selection transistor is connected to a word line (W5), which extends crosswise in relation to the bit line (B5). A diode of the image sensor is switched between a gate electrode (G5) of the memory transistor and a first source/drain area (S/D5) of the memory transistor, which is connected to the selection transistor in such a way is polarized towards the first source/drain area (S/D5) of the memory transistor and in the reverse direction. A photodiode of the image sensor is switched between a voltage connection and either the gate electrode (G5) of the memory transistor or the first source/drain area (S/D5) of the memory transistor in such a way that it is polarized towards the voltage connection and in the reverse direction.
摘要翻译：图像传感器的存储晶体管和选择晶体管串联连接在位线（B 5）和基准线（R 5）之间。选择晶体管的栅电极连接到相对于位线（B 5）横向延伸的字线（W 5）。图像传感器的二极管在存储晶体管的栅电极（G 5）和存储晶体管的第一源极/漏极区域（S / D 5）之间切换，以这样的方式连接到选择晶体管朝向存储晶体管的第一源极/漏极区域（S / D 5）偏振并且沿相反方向偏振。图像传感器的光电二极管在存储晶体管的栅电极（G 5）或存储晶体管的第一源/漏区（S / D 5）的电压连接和栅极之间切换，使得其被极化朝向电压连接和相反方向。

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