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    • 21. 发明授权
    • Automatic continuous tuning control apparatus for a receiver
    • 用于接收机的自动连续调谐控制装置
    • US4476580A
    • 1984-10-09
    • US272088
    • 1981-06-10
    • Kouji TanakaOsamu IkedaYoshio Nakayama
    • Kouji TanakaOsamu IkedaYoshio Nakayama
    • H03J1/00H03J5/02H03J7/22
    • H03J1/005H03J5/0281
    • A tuning control apparatus of a receiver having an electronic tuner comprises a tuning voltage generating circuit including a window comparator, a charge pump and a low-pass filter. An S curve signal is applied to the window comparator to make a search controlled by means of a voltage synthesizer system using the S curve signal until the receipt of a broadcasting signal. If an optimum tuning point is established through the search control, the local oscillation frequency at that time is counted to provide frequency division ratio data. A phase-locked loop is operated as a function of the frequency division ratio data on the occasion of the above described optimum tuning point, whereby reception of the broadcasting signal is continued. Preferably, an automatic frequency control operation is performed before the phase-locked loop is operated.
    • 具有电子调谐器的接收机的调谐控制装置包括具有窗口比较器,电荷泵和低通滤波器的调谐电压产生电路。 S曲线信号被施加到窗口比较器,以通过使用S曲线信号的电压合成器系统进行搜索控制,直到接收到广播信号。 如果通过搜索控制建立最佳调谐点,则计算当时的本地振荡频率以提供分频比数据。 在上述最佳调谐点的情况下,锁相环作为分频比数据的函数进行操作,从而继续接收广播信号。 优选地,在锁相环操作之前执行自动频率控制操作。
    • 22. 发明授权
    • Container device for planar battery
    • 平面电池容器装置
    • US4436792A
    • 1984-03-13
    • US440423
    • 1982-11-09
    • Naoki TominoOsamu IkedaYoshio MatsuzawaHideya Inoue
    • Naoki TominoOsamu IkedaYoshio MatsuzawaHideya Inoue
    • H01M2/10H01M6/46
    • H01M6/46H01M2/1066
    • A device capable of containing at least one planar battery having a positive electrode and a negative electrode and capable of supplying a power to a circuit when the battery has been completely contained includes a plurality of terminals for contacting the positive electrode and the negative electrode, respectively, of the battery when completely contained, means for holding each of the terminals, the holding means holding at least one of the terminals movably between a first position and a second position and wherein the movable terminal, when in the first position, contacts neither of the positive electrode and the negative electrode and, when in the second position, can contact one of the electrodes, and means for moving the movable terminal to the second position in response to the containment of the battery.
    • 一种能够容纳至少一个具有正极和负极的平面电池并且能够在电池完全容纳时向电路供电的装置分别包括用于接触正极和负极的多个端子 的电池,当完全容纳时,用于保持每个端子的装置,所述保持装置将至少一个端子可移动地保持在第一位置和第二位置之间,并且其中当处于第一位置时,可动端子既不接触 正极和负极,并且当处于第二位置时,可以接触电极中的一个,以及用于响应于电池容纳而将可动端子移动到第二位置的装置。
    • 25. 发明申请
    • GAME SYSTEM
    • 游戏系统
    • US20130274002A1
    • 2013-10-17
    • US13851871
    • 2013-03-27
    • Osamu Ikeda
    • Osamu Ikeda
    • A63F13/12
    • A63F13/85A63F13/12A63F13/75A63F2300/575
    • One object is to provide a game system that can technically restrain real money trade. In accordance with one aspect, a game system according to an embodiment of the present invention includes: a bid data generating unit configured to generate bid data including game medium information related to a bid game medium and not including player specifying information that specifies a bidder player; and a second display control unit configured to allow a bid screen generated based on bid data to be displayed in the game being played by an exhibitor player.
    • 一个目标是提供一个可以在技术上限制实际货币交易的游戏系统。 根据一个方面,根据本发明的实施例的游戏系统包括:投标数据生成单元,被配置为生成包括与投标游戏介质相关的游戏介质信息的投标数据,并且不包括指定投标人的玩家指定信息 ; 以及第二显示控制单元,被配置为允许在由参展者播放的游戏中显示基于投标数据生成的投标屏幕。
    • 29. 发明申请
    • NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    • 非易失性半导体存储器件
    • US20100224926A1
    • 2010-09-09
    • US12563287
    • 2009-09-21
    • Masanori HATAKEYAMAOsamu Ikeda
    • Masanori HATAKEYAMAOsamu Ikeda
    • H01L27/112
    • H01L27/11519H01L27/11521H01L27/11524
    • A plurality of NAND cells are arranged in a cell array. In each of the NAND cells, a pair of selection gate transistors is connected in series to a plurality of memory cell transistors. An inter-gate connection trench is formed in an insulating film between layers of stacked gates of the selection gate transistors. The stacked gates are electrically connected to each other. At an end part of the cell array in the row direction, an STI area is formed, and dummy NAND cells are formed at an end part in the row direction. A dummy selection gate transistor is connected in series to a plurality of dummy memory cell transistors. No inter-gate connection trench is present in an insulating film between layers of stacked gates of the dummy selection gate transistor, and the stacked gates of the dummy selection gate transistor are not electrically connected to each other.
    • 多个NAND单元被布置在单元阵列中。 在每个NAND单元中,一对选择栅极晶体管串联连接到多个存储单元晶体管。 在选择栅极晶体管的堆叠栅极的层之间的绝缘膜中形成栅极间连接沟槽。 堆叠的栅极彼此电连接。 在行方向的单元阵列的端部,形成STI区域,并且在行方向的端部形成虚拟NAND单元。 虚设选择栅极晶体管与多个虚设存储单元晶体管串联连接。 在虚拟选择栅极晶体管的堆叠栅极的层之间的绝缘膜中不存在栅极间连接沟槽,并且虚设选择栅极晶体管的堆叠栅极彼此不电连接。