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21. 发明申请

US20050169043A1 Semiconductor memory device and its manufacturing method 审中-公开
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20050169043A1
公开(公告)日：2005-08-04
申请号：US11046269
申请日：2005-01-27
申请人： Takashi Yokoyama , Takuji Tanigami
发明人： Takashi Yokoyama , Takuji Tanigami
IPC分类号： G11C13/00 , H01L21/8229 , H01L27/10 , H01L27/24 , H01L45/00 , H01L49/02 , G11C11/00
CPC分类号： H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A semiconductor memory device comprises a memory array on a semiconductor substrate having a constitution such that a plurality of memory cells where one end of the variable resistive element is connected to either an emitter or a collector of a bipolar transistor are arranged in the row and the column directions in a matrix form, the other of the emitter or the collector of the bipolar transistor in each memory cell in the same column is connected to common source line extending in the column direction, a base of the bipolar transistor in each memory cell in the same row is connected to common word line extending in the row direction, the other end of the variable resistive element in each memory cell in the same column is connected to common bit line extending in the column direction.
摘要翻译：半导体存储器件包括半导体衬底上的存储器阵列，其具有这样的结构，使得可变电阻元件的一端连接到双极晶体管的发射极或集电极的多个存储单元布置在行中，并且矩阵形式的列方向，同一列中的每个存储单元中的双极晶体管的发射极或集电极中的另一个连接到沿列方向延伸的公共源极线，每个存储单元中的双极晶体管的基极相同的行连接到在行方向上延伸的公共字线，同一列中每个存储单元中的可变电阻元件的另一端连接到在列方向上延伸的公共位线。

22. 发明申请

US20100034455A1 SOLAR BATTERY MODULE EVALUATION APPARATUS, SOLAR BATTERY MODULE EVALUATING METHOD, AND SOLAR BATTERY MODULE MANUFACTURING METHOD 审中-公开
标题翻译：太阳能电池模块评估装置，太阳能电池模块评估方法和太阳能电池模块制造方法
公开(公告)号：US20100034455A1
公开(公告)日：2010-02-11
申请号：US12298857
申请日：2007-04-16
申请人： Takashi Harada , Masahiro Ohbasami , Yoshinobu Umetani , Yoshio Katayama , Takuji Tanigami
发明人： Takashi Harada , Masahiro Ohbasami , Yoshinobu Umetani , Yoshio Katayama , Takuji Tanigami
IPC分类号： G06K9/00
CPC分类号： G01N21/9501 , G01N21/66 , H01L31/186 , H02S40/34 , H02S50/10 , Y02E10/50 , Y02P70/521
摘要： Management of a manufacturing process also in assembling a solar battery module is facilitated. A solar battery module evaluation apparatus includes a power supply unit, a camera, and a processing unit. The power supply unit supplies electric power. The processing unit outputs pattern information indicating whether a solar battery module is defective or not, based on data of an image picked up by the camera, the image being an optical image that appears as a result of supply of electric power to the solar battery module for light emission through electroluminescence phenomenon.
摘要翻译：便于组装太阳能电池模块的制造过程的管理。太阳能电池模块评估装置包括电源单元，照相机和处理单元。电源单元供电。处理单元基于由照相机拍摄的图像的数据输出指示太阳能电池模块是否有故障的图案信息，作为向太阳能电池模块供电的结果而出现的光学图像的图像用于通过电致发光现象发光。

23. 发明授权

US06589844B2 Process for manufacturing semiconductor memory device having floating and control gates in which multiple insulating films are formed over floating gates 有权
标题翻译：具有浮置和控制栅极的半导体存储器件的制造方法，其中在浮栅上形成多个绝缘膜
公开(公告)号：US06589844B2
公开(公告)日：2003-07-08
申请号：US10153728
申请日：2002-05-24
申请人： Takuji Tanigami
发明人： Takuji Tanigami
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A process for manufacturing a semiconductor memory device comprises the steps of: (a) forming a tunnel oxide film, a first (1st) conductive film to be a lower floating gate, a 1st insulating film and a second (2nd) insulating film in this order on a semiconductor substrate and patterning the 2nd insulating film, the 1st insulating film, the 1st conductive film and the tunnel oxide film into a desired configuration; (b) forming a third (3rd) insulating film on the entire surface of the resulting substrate; (c) reducing the 3rd insulating film until the 2nd insulating film is exposed; (d) removing the 2nd insulating film; (e) removing the 1st insulating film while further reducing the 3rd insulating film; (f) forming a 2nd conductive film to be an upper floating gate on the 1st conductive film and the 3rd insulating film; (g) flattening the 2nd conductive film until the 3rd insulating film is exposed; and (h) forming an interlayer capacitance film and a 3rd conductive film to be a control gate on the 2nd conductive film and the 3rd insulating film, and patterning the 3rd conductive film, the interlayer capacitance film, the 2nd conductive film and the 1st conductive film to form a floating gate and the control gate.
摘要翻译：一种制造半导体存储器件的方法包括以下步骤：（a）在其中形成隧道氧化物膜，第一（第一）导电膜作为下浮动栅极，第一绝缘膜和第二绝缘膜（第二绝缘膜）将第二绝缘膜，第一绝缘膜，第一导电膜和隧道氧化物膜图案化成期望的构造; （b）在所得基板的整个表面上形成第三（第三）绝缘膜; （c）减少第三绝缘膜，直到暴露第二绝缘膜; （d）除去第二绝缘膜; （e）在进一步减少第三绝缘膜的同时去除第一绝缘膜; （f）在第一导电膜和第三绝缘膜上形成第二导电膜作为上浮置栅; （g）使第二导电膜平坦化，直到暴露第三绝缘膜; 和（h）在第二导电膜和第三绝缘膜上形成层间电容膜和第三导电膜作为控制栅极，并且对第三导电膜，层间电容膜，第二导电膜和第一导电膜电影形成一个浮动门和控制门。

24. 发明授权

US06544843B2 Process for manufacturing semiconductor device 失效
标题翻译：半导体器件制造工艺
公开(公告)号：US06544843B2
公开(公告)日：2003-04-08
申请号：US09738637
申请日：2000-12-18
申请人： Takuji Tanigami
发明人： Takuji Tanigami
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , G11C16/0491 , H01L21/76819 , H01L27/115
摘要： A process for manufacturing a semiconductor device forming a plurality of protrusions with different widths so that a recess between adjacent protrusions has a predetermined width on a semiconductor substrate and thereafter forming an insulating layer for element isolation in the recess, wherein the insulating layer for element isolation is formed by the steps of: (A) filling an insulating film for forming the insulating layer for element isolation in the recess to a higher level than top surfaces of the protrusions; (B) removing the insulating film at least from a top surface of a narrow protrusion and etching back the insulating film in the recess to a level lower than the top surface of the narrow protrusion, thereby exposing the top surface and a side face of the narrow protrusion and a side face and a part of a top face next to the side face of a wide protrusion; and (C) forming a mask to cover the exposed top surfaces and side faces of the protrusions and the top surface of the insulating film in the recess, removing the insulating film remaining from the top surface of the wide protrusion, and removing the mask, thereby forming the insulating layer for element isolation in the recess.
摘要翻译：一种用于制造形成具有不同宽度的多个突起的半导体器件的方法，使得相邻突起之间的凹部在半导体衬底上具有预定宽度，然后在凹部中形成用于元件隔离的绝缘层，其中用于元件隔离的绝缘层通过以下步骤形成：（A）将用于在凹部中形成用于元件隔离的绝缘层的绝缘膜填充到比突起的顶表面更高的水平;（B）至少从顶表面去除绝缘膜，一个狭窄的突出部分并且将凹陷中的绝缘膜蚀刻回到比该窄突起的顶表面低的水平面上，从而暴露该窄突起的顶表面和一个侧面以及一顶面的一个侧面和一部分到广泛突起的侧面; 和（C）形成掩模以覆盖突出部的暴露的顶表面和侧面以及凹部中的绝缘膜的顶表面，去除从宽突起的顶表面残留的绝缘膜，并且去除掩模，从而在凹部中形成用于元件隔离的绝缘层。

25. 发明授权

US5742541A Writing method for nonvolatile semiconductor memory with soft-write repair for over-erased cells 失效
标题翻译：非易失性半导体存储器的写入方法，具有用于超擦除单元的软写修复
公开(公告)号：US5742541A
公开(公告)日：1998-04-21
申请号：US580515
申请日：1995-12-28
申请人： Takuji Tanigami , Shinichi Sato
发明人： Takuji Tanigami , Shinichi Sato
IPC分类号： G11C17/00 , G11C16/04 , G11C16/10 , G11C16/14 , G11C16/34
CPC分类号： G11C16/3409 , G11C16/0416 , G11C16/10 , G11C16/14 , G11C16/3404
摘要： A non-volatile semiconductor memory includes a plurality of memory cells. Each memory cell includes N-type source and drain regions formed in a P-well on a semiconductor substrate, a floating gate formed on the P-well with a tunnel oxide film therebetween, and a control gate formed on the floating gate with an interpoly dielectric film therebetween. The memory has a plurality of bit lines, a plurality of word lines and a source line. The source region of each memory cell is connected to the source line. The drain region of each memory cell is connected to one of the word lines. The memory cell is written to, erased, or read by selectively supplying suitable voltages to the source, bit, and word lines connected thereto. When a selected memory cell is written to by injection electrons into its floating gate, (1) a negative voltage is applied to the P-well and the source line, (2) a first positive voltage is applied to the selected bit line, (3) a second positive voltage is applied to the selected word line, and (4) OV is applied to the non-selected word line. The second positive voltage applied to the control gate is lower than a predetermined voltage between the source and the control gate.
摘要翻译：非易失性半导体存储器包括多个存储单元。每个存储单元包括形成在半导体衬底上的P阱中的N型源极和漏极区，在P阱上形成有在其间具有隧道氧化物膜的浮置栅极，以及在浮置栅极上形成的具有间隔电介质膜之间。存储器具有多个位线，多个字线和源极线。每个存储单元的源区连接到源极线。每个存储单元的漏极区域连接到一条字线。通过向连接到其的源，位和字线选择性地提供合适的电压来将存储单元写入，擦除或读取。当通过注入电子将选定的存储单元写入其浮动栅极时，（1）向P阱和源极线施加负电压，（2）将第一正电压施加到所选位线， 3）将第二正电压施加到所选字线，并且（4）将OV施加到未选择的字线。施加到控制栅极的第二正电压低于源极和控制栅极之间的预定电压。

26. 发明授权

US6069041A Process for manufacturing non-volatile semiconductor memory device by introducing nitrogen atoms 失效
标题翻译：通过引入氮原子制造非易失性半导体存储器件的方法
公开(公告)号：US6069041A
公开(公告)日：2000-05-30
申请号：US974158
申请日：1997-11-19
申请人： Takuji Tanigami , Shinichi Sato , Kenichi Azuma
发明人： Takuji Tanigami , Shinichi Sato , Kenichi Azuma
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28176 , H01L21/28273 , H01L29/511 , H01L29/518 , H01L21/28194 , Y10S438/91
摘要： A process for manufacturing a non-volatile semiconductor memory device by forming a tunnel dielectric film, a floating gate electrode, an interlayer capacitive film and a control gate electrode successively on a semiconductor substrate includes introducing nitrogen atoms into at least one of an interface between the floating gate electrode and the interlayer capacitive film and an interface between the interlayer capacitive film and the control gate electrode.
摘要翻译：通过在半导体衬底上依次形成隧道电介质膜，浮栅电极，层间电容膜和控制栅电极来制造非易失性半导体存储器件的工艺包括将氮原子引入至少一个浮栅电极和层间电容膜以及层间电容膜和控制栅电极之间的界面。

27. 发明申请

US20130026844A1 PHOTOVOLTAIC GENERATION SYSTEM, POWER CONVERSION DEVICE, AND COLLECTOR BOX 审中-公开
标题翻译：光伏发电系统，电力转换装置和收集箱
公开(公告)号：US20130026844A1
公开(公告)日：2013-01-31
申请号：US13640898
申请日：2011-03-25
申请人： Hirofumi Mitsuoka , Takuji Tanigami
发明人： Hirofumi Mitsuoka , Takuji Tanigami
IPC分类号： H02J3/38
CPC分类号： H02J3/383 , H01L31/02021 , Y02B10/14 , Y02E10/563 , Y02P80/23 , Y10T307/707
摘要： A photovoltaic generation system includes: a solar cell array that includes a plurality of solar cell modules; a collector portion that collects power from the solar cell array; a power control portion that is connected to the collector portion and includes a power conversion portion which converts first power from the solar cell array into second power; a first electric wiring that connects the collector portion and the power control portion to each other; a first connection terminal that is supplied with the first power from the solar cell array; and a first switch portion that shuts off output from the solar cell array for the power conversion portion; wherein an alternative power control portion is connectable to the first connection terminal.
摘要翻译：光伏发电系统包括：太阳能电池阵列，其包括多个太阳能电池模块; 从太阳能电池阵列收集电力的收集器部分; 功率控制部分，其连接到集电器部分，并且包括将来自太阳能电池阵列的第一功率转换为第二功率的功率转换部分; 将所述集电部和所述电力控制部彼此连接的第一电布线; 从太阳能电池阵列提供第一功率的第一连接端子; 以及切断用于所述电力转换部的所述太阳能电池阵列的输出的第一开关部; 其中替代功率控制部分可连接到所述第一连接端子。

28. 发明授权

US06395619B2 Process for fabricating a semiconductor device 有权
标题翻译：制造半导体器件的工艺
公开(公告)号：US06395619B2
公开(公告)日：2002-05-28
申请号：US09203330
申请日：1998-12-02
申请人： Takuji Tanigami , Kenji Hakozaki , Naoyuki Shinmura , Shinichi Sato , Masanori Yoshimi , Takayuki Taniguchi
发明人： Takuji Tanigami , Kenji Hakozaki , Naoyuki Shinmura , Shinichi Sato , Masanori Yoshimi , Takayuki Taniguchi
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： The present invention provides a process for fabricating semiconductor device comprising the steps of: forming an etching-stop layer on a semiconductor substrate; patterning the etching-stop layer so that the etching-stop layer remains in a region to be an active region and is removed from a region to be a device isolation region, followed by forming a trench in the region to be the device isolation region; depositing on the semiconductor substrate an insulating film having a thickness greater than or equal to the depth of the trench; forming a resist pattern having an opening above the etching-stop layer above the active region adjacent to a device isolation region whose width is greater than or equal to a predetermined value, followed by etching the insulating film using the resist pattern as a mask; and polishing the insulating film existing on the resulting semiconductor substrate for flattening after removing the resist pattern.
摘要翻译：本发明提供一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成蚀刻停止层; 图案化蚀刻停止层，使得蚀刻停止层保持在作为有源区的区域中，并从作为器件隔离区的区域去除，然后在该区域中形成作为器件隔离区的沟槽; 在半导体衬底上沉积厚度大于或等于沟槽深度的绝缘膜; 形成抗蚀剂图案，其具有在与宽度大于或等于预定值的器件隔离区相邻的有源区上方的蚀刻停止层上方的开口，然后使用抗蚀剂图案作为掩模蚀刻绝缘膜; 并且在除去抗蚀剂图案之后，对存在于所得半导体衬底上的绝缘膜进行抛光以使其变平。

29. 发明授权

US5708600A Method for writing multiple value into nonvolatile memory in an equal time 失效
标题翻译：在同一时间内将多个值写入非易失性存储器的方法
公开(公告)号：US5708600A
公开(公告)日：1998-01-13
申请号：US725661
申请日：1996-10-01
申请人： Kenji Hakozaki , Shinichi Sato , Takuji Tanigami
发明人： Kenji Hakozaki , Shinichi Sato , Takuji Tanigami
IPC分类号： G11C17/00 , G11C11/56 , G11C16/02
CPC分类号： G11C11/5628 , G11C11/5621
摘要： There is provided a method for writing a multiple value into a nonvolatile memory capable of writing multiple value data into a floating gate type memory cell in an equal time even when the data are varied. With a specified voltage applied to a control gate of a memory cell, a drain voltage which is varied according to each of data values "11", "10" and "01" to a drain so that a write time required for setting a varied threshold voltage is equalized. By moving electrons between a floating gate and a drain through a gate insulating film, the threshold voltage of the memory cell is set.
摘要翻译：提供了一种用于将多值写入非易失性存储器的方法，该非易失性存储器能够在相等的时间内将多值数据写入浮置型存储单元，即使数据变化。利用施加到存储单元的控制栅极的指定电压，将漏极电压根据数据值“11”，“10”和“01”中的每一个变化到漏极，使得设置变化的所需的写入时间阈值电压相等。通过栅极绝缘膜在浮置栅极和漏极之间移动电子，设定存储单元的阈值电压。

30. 发明授权

US06441430B1 Semiconductor device with floating gates 有权
标题翻译：具有浮动栅极的半导体器件
公开(公告)号：US06441430B1
公开(公告)日：2002-08-27
申请号：US09588761
申请日：2000-06-06
申请人： Takuji Tanigami
发明人： Takuji Tanigami
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device including a plurality of floating gates where each floating gate includes a lower floating gate whose sidewalls are substantially vertical to the semiconductor substrate and an upper floating gate having opposing sidewall portions that gradually widen in a convex manner towards the top of the floating gate. The device further includes an interlayer insulating film, and a control gate formed on the insulating film. An insulating film (10) is provided between and contacting adjacent floating gates, and has vertically aligned lower sidewall portions which contact the lower floating gates and curved upper sidewall portions which contact the upper floating gates and gradually narrow toward the top of the insulating film.
摘要翻译：一种包括多个浮动栅极的半导体器件，其中每个浮置栅极包括其侧壁基本上垂直于半导体衬底的下部浮置栅极，以及具有相对侧壁部分的上部浮动栅极，所述相对的侧壁部分以凸形方式朝向浮动栅极的顶部逐渐变宽。该器件还包括层间绝缘膜和形成在绝缘膜上的控制栅极。绝缘膜（10）设置在相邻的浮动栅极之间并与之相接触，并且具有垂直对准的下侧壁部分，该下侧壁部分接触下浮动栅极和弯曲的上侧壁部分，该上侧壁部分与上浮动栅极接触，并朝向绝缘膜的顶部逐渐变窄。

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