专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20080297220A1 Method of forming a CMOS structure having gate insulation films of different thicknesses 有权
公开(公告)号：US20080297220A1
公开(公告)日：2008-12-04
申请号：US12153385
申请日：2008-05-19
申请人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
发明人： Nozomu Matsuzaki , Hiroyuki Mizuno , Masashi Horiguchi
IPC分类号： H03K3/356
CPC分类号： H01L21/823857 , B82Y99/00 , H01L21/82345 , H01L21/823462 , H01L21/823468 , H01L21/82385 , H01L27/088 , H01L27/0883 , H01L29/42364 , Y10S438/981 , Y10S977/936
摘要： The semiconductor integrated circuit device employs on the same silicon substrate a plurality of kinds of MOS transistors with different magnitudes of tunnel current flowing either between the source and gate or between the drain and gate thereof. These MOS transistors include tunnel-current increased MOS transistors at least one of which is for use in constituting a main circuit of the device. The plurality of kinds of MOS transistors also include tunnel-current reduced or depleted MOS transistors at least one of which is for use with a control circuit. This control circuit is inserted between the main circuit and at least one of the two power supply units.

22. 发明申请

US20070170413A1 Semiconductor memory 审中-公开
标题翻译：半导体存储器
公开(公告)号：US20070170413A1
公开(公告)日：2007-07-26
申请号：US11596220
申请日：2005-05-09
申请人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
发明人： Yuichi Matsui , Nozomu Matsuzaki , Norikatsu Takaura , Naoki Yamamoto , Hideyuki Matsuoka , Tomio Iwasaki
IPC分类号： H01L29/04
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/12 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.
摘要翻译：由于这种材料对高熔点金属和氧化硅膜具有低粘附性，所以相变存储器的制造过程已经受到硫属化物材料易于分层的问题的困扰。此外，硫族化物材料具有低的热稳定性，因此在相变存储器的制造过程中倾向于升华。根据本发明，在硫族化物材料层上和下方形成导电或绝缘粘合剂层以增强其分层强度。此外，在硫族化物材料层的侧壁上形成由氮化物膜构成的保护膜，以防止硫属化物材料层的升华。

23. 发明申请

US20070159871A1 Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
标题翻译：具有不可擦除存储器和/或非易失性存储器的半导体器件
公开(公告)号：US20070159871A1
公开(公告)日：2007-07-12
申请号：US11715918
申请日：2007-03-09
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C16/06 , G11C11/34 , G11C7/10 , G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译：一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

24. 发明授权

US07206216B2 Semiconductor device with a non-erasable memory and/or a nonvolatile memory 失效
公开(公告)号：US07206216B2
公开(公告)日：2007-04-17
申请号：US11057682
申请日：2005-02-15
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.

25. 发明授权

US07130223B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07130223B2
公开(公告)日：2006-10-31
申请号：US11251963
申请日：2005-10-18
申请人： Tetsuya Ishimaru , Nozomu Matsuzaki , Hitoshi Kume
发明人： Tetsuya Ishimaru , Nozomu Matsuzaki , Hitoshi Kume
IPC分类号： G11C11/34
CPC分类号： G11C16/0433 , G11C16/0466 , G11C16/10 , G11C16/14 , H01L27/11568 , H01L29/513 , H01L29/518 , H01L29/792
摘要： Characteristics of a nonvolatile semiconductor memory device are improved. The memory cell comprises: an ONO film constituted by a silicon nitride film SIN for accumulating charge and by oxide films BOTOX and TOPOX disposed thereon and thereunder; a memory gate electrode MG disposed at an upper portion thereof; a select gate electrode SG disposed at a side portion thereof through the ONO film; a gate oxide film SGOX disposed thereunder. By applying a potential to a select gate electrode SG of a memory cell having a source region MS and a drain region MD and to the source region MS and by accelerating electrons flowing in a channel through a high electric field produced between a channel end of the select transistor and an end of an n-type doped region ME disposed under the memory gate electrode MG, hot holes are generated by impact ionization, and the hot holes are injected into a silicon nitride film SIN by a negative potential applied to the memory gate electrode MG, and thereby an erase operation is performed.
摘要翻译：提高了非易失性半导体存储器件的特性。存储单元包括：由用于累积电荷的氮化硅膜SIN和其上设置的氧化膜BOTOX和TOPOX构成的ONO膜; 设置在其上部的存储栅极电极MG; 通过ONO膜设置在其侧部的选择栅电极SG; 设置在其下方的栅氧化膜SGOX。通过向具有源极区域MS和漏极区域MD的存储单元的选择栅极SG施加电位，并且通过在通道的沟道端之间产生的高电场加速在沟道中流动的电子，选择晶体管和设置在存储栅电极MG下方的n型掺杂区ME的端部，通过冲击电离产生热孔，并且通过施加到存储栅的负电位将热孔注入氮化硅膜SIN 电极MG，从而进行擦除操作。

26. 发明申请

US20050185445A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050185445A1
公开(公告)日：2005-08-25
申请号：US11057682
申请日：2005-02-15
申请人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
发明人： Kenichi Osada , Riichiro Takemura , Norikatsu Takaura , Nozomu Matsuzaki , Takayuki Kawahara
IPC分类号： G11C13/00 , G06F13/00 , G11C11/00 , G11C16/02 , G11C16/10 , G11C16/26 , G11C16/34 , G11C19/08 , H01L27/10 , H01L27/105
CPC分类号： G11C13/0004 , G11C13/0033 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C16/3454 , G11C2013/0092 , G11C2213/82
摘要： A semiconductor device comprises a plurality of memory cells, a central processing unit, a timer circuit which times a RESET time, and a timer circuit which times a SET time. A threshold voltage of an NMOS transistor of each memory cell is lower than that of the peripheral circuit, thereby easily executing a RESET operation. The direction of a flowing current is changed across the RESET operation and the SET operation, and the bit lines are activated at high speed, thus preventing system malfunctions. Further, the semiconductor device can overcome such problems as a wrong write operation and data destruction, resulting from the variation in the CMOS transistors when operating phase change elements with minimum size CMOS transistors at a core voltage (e.g. 1.2 V). According to the present invention, stable operations can be realized at a low voltage, using minimum-size cell transistors.
摘要翻译：一种半导体器件包括多个存储单元，一个中央处理单元，一个复位时间的定时器电路，以及一个定时器电路，该定时器电路需要一个SET时间。每个存储单元的NMOS晶体管的阈值电压低于外围电路的阈值电压，从而容易地执行复位操作。流过电流的方向在复位操作和SET操作中改变，位线被高速激活，从而防止系统故障。此外，半导体器件可以克服由于核心电压（例如1.2V）下操作具有最小尺寸CMOS晶体管的相位变化元件时CMOS晶体管的变化而导致的错误写入操作和数据破坏的问题。根据本发明，可以使用最小尺寸的单元晶体管在低电压下实现稳定的操作。

27. 发明授权

US06711061B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06711061B2
公开(公告)日：2004-03-23
申请号：US10223488
申请日：2002-08-20
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

28. 发明申请

US20120286225A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120286225A1
公开(公告)日：2012-11-15
申请号：US13541097
申请日：2012-07-03
申请人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。

29. 发明授权

US08084810B2 Fabrication method and structure of semiconductor non-volatile memory device 有权
标题翻译：半导体非易失性存储器件的制造方法和结构
公开(公告)号：US08084810B2
公开(公告)日：2011-12-27
申请号：US12648796
申请日：2009-12-29
申请人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
发明人： Digh Hisamoto , Shinichiro Kimura , Kan Yasui , Nozomu Matsuzaki
IPC分类号： H01L21/336
CPC分类号： H01L27/11531 , H01L21/28282 , H01L27/115 , H01L27/11526 , H01L27/11546 , H01L27/11568 , H01L29/42344 , H01L29/792
摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.
摘要翻译：提供具有良好写入/擦除特性的非易失性半导体存储器件。通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极氧化硅膜。存储器栅极通过层叠膜与选择栅极相邻。在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

30. 发明授权

US07884348B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07884348B2
公开(公告)日：2011-02-08
申请号：US12754049
申请日：2010-04-05
申请人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L29/02 , H01L31/032
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞和堆叠在其上的插头。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式