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21. 发明申请

US20100006812A1 CARBON-BASED RESISTIVITY-SWITCHING MATERIALS AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：基于碳的电阻率切换材料及其形成方法
公开(公告)号：US20100006812A1
公开(公告)日：2010-01-14
申请号：US12499467
申请日：2009-07-08
申请人： Huiwen Xu , Xiying Chen , Roy E. Scheuerlein , Er-Xuan Ping , Tanmay Kumar , Alper Ilkbahar
发明人： Huiwen Xu , Xiying Chen , Roy E. Scheuerlein , Er-Xuan Ping , Tanmay Kumar , Alper Ilkbahar
IPC分类号： H01L29/02 , H01L21/00
CPC分类号： B82Y10/00 , B82Y30/00 , C23C16/26 , G11C13/0014 , G11C13/025 , G11C2213/19 , G11C2213/35 , G11C2213/71 , G11C2213/72 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/124 , H01L45/149 , H01L45/1616
摘要： Memory devices including a carbon-based resistivity-switchable material, and methods of forming such memory devices are provided, the methods including introducing a processing gas into a processing chamber, wherein the processing gas includes a hydrocarbon compound and a carrier gas, and generating a plasma of the processing gas to deposit a layer of the carbon-based switchable material on a substrate within the processing chamber. Numerous additional aspects are provided.
摘要翻译：提供了包括碳基电阻率可切换材料的存储器件以及形成这种存储器件的方法，所述方法包括将处理气体引入处理室，其中所述处理气体包括烃化合物和载气，并且产生处理气体的等离子体，以将一层碳基可切换材料沉积在处理室内的基板上。还提供了许多其他方面。

22. 发明申请

US20090268508A1 Reverse leakage reduction and vertical height shrinking of diode with halo doping 有权
标题翻译：具有晕圈掺杂的二极管的反向泄漏减小和垂直高度收缩
公开(公告)号：US20090268508A1
公开(公告)日：2009-10-29
申请号：US12149217
申请日：2008-04-29
申请人： Xiying Chen , Mark H. Clark , S. Brad Herner , Tanmay Kumar
发明人： Xiying Chen , Mark H. Clark , S. Brad Herner , Tanmay Kumar
IPC分类号： G11C11/34 , H01L21/34 , G11C11/00 , H01L29/868
CPC分类号： H01L29/868 , H01L29/1606 , H01L29/8615
摘要： One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.
摘要翻译：本发明的一个实施例提供一种半导体二极管器件，其包括第一导电类型区域和第二导电类型区域，其中第二导电类型不同于第一导电类型，位于第一导电类型区域和第二导电类型之间的本征区域类型区域位于第二导电类型区域和本征区域之间的第一导电类型的第一晕区，以及任选地位于第一导电类型区域和本征区域之间的第二导电类型的第二晕区域。

23. 发明申请

US20090258489A1 Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same 有权
标题翻译：含有碳储存材料的多层非易失性存储器件及其制造和使用方法
公开(公告)号：US20090258489A1
公开(公告)日：2009-10-15
申请号：US12153874
申请日：2008-05-27
申请人： Xiying Chen , Chuanbin Pan , Tanmay Kumar , Er-Xuan Ping
发明人： Xiying Chen , Chuanbin Pan , Tanmay Kumar , Er-Xuan Ping
IPC分类号： H01L21/44
CPC分类号： H01L27/1021 , H01L27/101 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/124 , H01L45/149 , H01L45/1616 , H01L45/1675
摘要： A method of making a non-volatile memory device includes forming a first electrode, forming a steering element, forming at least one feature, forming a carbon resistivity switching material on at least one sidewall of the at least one feature such that the carbon resistivity switching material electrically contacts the steering element, and forming a second electrode.
摘要翻译：制造非易失性存储器件的方法包括形成第一电极，形成转向元件，形成至少一个特征，在至少一个特征的至少一个侧壁上形成碳电阻率切换材料，使得碳电阻率切换材料电接触转向元件，并形成第二电极。

24. 发明申请

US20090258135A1 Method of making nonvolatile memory cell containing carbon resistivity switching as a storage element by low temperature processing 有权
标题翻译：通过低温处理制造含有碳电阻率开关作为存储元件的非易失性存储单元的方法
公开(公告)号：US20090258135A1
公开(公告)日：2009-10-15
申请号：US12222341
申请日：2008-08-07
申请人： Tanmay Kumar , Er-Xuan Ping , Alper Ilkbahar
发明人： Tanmay Kumar , Er-Xuan Ping , Alper Ilkbahar
IPC分类号： B05D5/12
CPC分类号： H01L45/04 , G11C13/00 , H01L27/2409 , H01L45/1233 , H01L45/149 , H01L45/1608
摘要： A method of making a nonvolatile memory cell includes forming a steering element and forming a carbon resistivity switching material storage element by coating a carbon containing colloid.
摘要翻译：制造非易失性存储单元的方法包括：通过涂覆含碳胶体形成转向元件并形成碳电阻率切换材料储存元件。

25. 发明申请

US20080025078A1 SYSTEMS FOR REVERSE BIAS TRIM OPERATIONS IN NON-VOLATILE MEMORY 有权
标题翻译：用于在非易失性存储器中反向偏移操作的系统
公开(公告)号：US20080025078A1
公开(公告)日：2008-01-31
申请号：US11461431
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tanmay Kumar
发明人： Roy E. Scheuerlein , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C5/02 , G11C11/56 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C17/16 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
摘要翻译：公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以在第二电阻电平处的第一电阻电平将其电阻从设定状态改变为复位状态。复位的一组单元格中的某些存储单元可能被重新设置为超出复位状态的目标电平的电阻水平。第二反向偏压被施加到存储器单元组，以将每个单元的电阻移动到复位状态的目标电平。与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并脱离它们的深度复位状态。操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。未重新设置的单元格不受影响。

26. 发明申请

US20060221758A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：US20060221758A1
公开(公告)日：2006-10-05
申请号：US11420787
申请日：2006-05-29
申请人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

27. 发明授权

US08946673B1 Resistive switching device structure with improved data retention for non-volatile memory device and method 有权
标题翻译：电阻式开关器件结构具有改进的非易失性存储器件的数据保持和方法
公开(公告)号：US08946673B1
公开(公告)日：2015-02-03
申请号：US13594665
申请日：2012-08-24
申请人： Tanmay Kumar
发明人： Tanmay Kumar
IPC分类号： H01L47/00
CPC分类号： H01L45/148 , H01L45/085 , H01L45/1233 , H01L45/1253
摘要： A non-volatile memory device structure includes a first conductor extending in a first direction, a second conductor extending in a second direction approximately orthogonal to the first direction, an amorphous silicon material disposed in an intersection between the first and second conductors characterized by a first resistance upon application of a first voltage, wherein the first resistance is dependent on a conductor structure comprising material from the second conductor formed in a portion of the resistive switching material, and a layer of material configured in between the second conductor and the amorphous silicon material, wherein the layer maintains at least a portion the conductor structure in the amorphous silicon material, and wherein the layer inhibits conductor species from the portion of the conductor structure from migrating away from the second conductor when a second voltage having an amplitude less than the first voltage is applied.
摘要翻译：非易失性存储器件结构包括沿第一方向延伸的第一导体，在大致正交于第一方向的第二方向上延伸的第二导体，设置在第一和第二导体之间的交叉点中的非晶硅材料，施加第一电压时的电阻，其中所述第一电阻取决于导体结构，所述导体结构包括来自形成在所述电阻开关材料的一部分中的所述第二导体的材料，以及配置在所述第二导体和所述非晶硅材料之间的材料层，其中所述层保持所述非晶硅材料中的导体结构的至少一部分，并且其中当所述第二电压具有小于所述第一导体结构的振幅的第二电压时，所述层抑制所述导体结构的所述部分中的导体种类离开所述第二导体迁移施加电压。

28. 发明授权

US08465996B2 Surface treatment to improve resistive-switching characteristics 有权
公开(公告)号：US08465996B2
公开(公告)日：2013-06-18
申请号：US13593116
申请日：2012-08-23
申请人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
发明人： Michael Miller , Prashant Phatak , Tony Chiang , Xiyang Chen , April Schricker , Tanmay Kumar
IPC分类号： H01L21/00
CPC分类号： H01L45/16 , H01L21/265 , H01L21/31155 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/12 , H01L45/1233 , H01L45/146 , H01L45/1608 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

29. 发明申请

US20130027081A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
标题翻译：现场可编程门阵列使用两端非易失性存储器
公开(公告)号：US20130027081A1
公开(公告)日：2013-01-31
申请号：US13194500
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/0944 , H03K19/177
CPC分类号： H03K19/0013 , G11C13/0002 , G11C13/004 , G11C13/0069 , H03K19/0944 , H03K19/1776 , H03K19/17764 , H03K19/17776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.
摘要翻译：本文描述了利用电阻随机存取存储器（RRAM）技术提供现场可编程门阵列（FPGA）。作为示例，FPGA可以包括具有由垂直信号输出线交叉的并行信号输入线的开关块互连。可以在信号输入线和信号输出线的各个交叉处形成RRAM存储器单元。 RRAM存储器单元可以包括分压器，该分压器包括跨FPGA的VCC和VSS串联电串联的多个可编程电阻元件。分压器的公共节点驱动配置为激活或去激活交叉的通路晶体管的栅极。所公开的RRAM存储器可以提供高晶体管密度，高逻辑利用率，快速的编程速度，辐射抗扰度，快速上电和对FPGA技术的显着益处。

30. 发明申请

US20130027079A1 FIELD PROGRAMMABLE GATE ARRAY UTILIZING TWO-TERMINAL NON-VOLATILE MEMORY 有权
公开(公告)号：US20130027079A1
公开(公告)日：2013-01-31
申请号：US13194479
申请日：2011-07-29
申请人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
发明人： Hagop Nazarian , Sang Thanh Nguyen , Tanmay Kumar
IPC分类号： H03K19/177 , G11C11/00 , H01L21/82
CPC分类号： H03K19/17776 , G11C13/0021 , H01L27/101 , H03K19/0013 , H03K19/00315 , H03K19/0944 , H03K19/1776
摘要： Providing for a field programmable gate array (FPGA) utilizing resistive random access memory (RRAM) technology is described herein. By way of example, the FPGA can comprise a switching block interconnect having parallel signal input lines crossed by perpendicular signal output lines. RRAM memory cells can be formed at respective intersections of the signal input lines and signal output lines. The RRAM memory cell can include a voltage divider comprising multiple programmable resistive elements arranged electrically in series across a VCC and VSS of the FPGA. A common node of the voltage divider drives a gate of a pass gate transistor configured to activate or deactivate the intersection. The disclosed RRAM memory can provide high transistor density, high logic utilization, fast programming speed, radiation immunity, fast power up and significant benefits for FPGA technology.

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