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21. 发明授权

US07974053B2 ESD protection circuit for differential I/O pair 有权
标题翻译：差分I / O对的ESD保护电路
公开(公告)号：US07974053B2
公开(公告)日：2011-07-05
申请号：US12129230
申请日：2008-05-29
申请人： Ming-Dou Ker , Yuan-Wen Hsiao , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Yuan-Wen Hsiao , Hsin-Chin Jiang
IPC分类号： H02H9/00 , H02H3/20 , H02H9/04
CPC分类号： H01L27/0251 , H03F1/523 , H03F3/45183
摘要： An ESD protection circuit for a differential I/O pair is provided. The circuit includes an ESD detection circuit, a discharge device, and four diodes. The first diode is coupled between the first I/O pin and the discharge device in a forward direction toward the discharge device. The second diode is coupled between the second I/O pin and the discharge device in a forward direction toward the second I/O pin. The third diode is coupled between the discharge device and the positive power line in a forward direction toward the positive power line. The fourth diode is coupled between the discharge device and the negative power line in a forward direction toward the discharge device. Via an output end, the ESD detection circuit triggers the discharge device during ESD events.
摘要翻译：提供了用于差分I / O对的ESD保护电路。该电路包括ESD检测电路，放电装置和四个二极管。第一二极管在朝向放电装置的正向方向上在第一I / O引脚和放电装置之间耦合。第二二极管在第二I / O引脚和放电装置之间朝向第二I / O引脚向前方连接。第三二极管朝着正电力线向前方连接在放电装置和正电力线之间。第四二极管在放电装置和负电源线之间朝向放电装置向前方连接。通过输出端，ESD检测电路在ESD事件期间触发放电装置。

22. 发明申请

US20100315754A1 TRANSIENT VOLTAGE DETECTION CIRCUIT 有权
标题翻译：瞬态电压检测电路
公开(公告)号：US20100315754A1
公开(公告)日：2010-12-16
申请号：US12625449
申请日：2009-11-24
申请人： Ming-Dou Ker , Wen-Yi Chen , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Wen-Yi Chen , Hsin-Chin Jiang
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H02H1/0007
摘要： The invention discloses a transient voltage detection circuit suitable for an electronic system. The electronic system includes a high voltage line and a low voltage line. The transient voltage detection circuit includes at least one detection circuit and a judge module. Each detection circuit includes a P-typed transistor and/or an N-typed transistor, a capacitor and a detection node. The transistor is coupled with the capacitor, and the detection node is located between the transistor and the capacitor. The judge module is coupled to each of the detection nodes. The judge module generates a judgment according to voltage levels of the detection nodes. Accordingly, the transient voltage detection circuit is formed. The electronic system may selectively execute a protective action according to the judgment.
摘要翻译：本发明公开了一种适用于电子系统的瞬态电压检测电路。电子系统包括高压线路和低压线路。瞬态电压检测电路包括至少一个检测电路和判断模块。每个检测电路包括P型晶体管和/或N型晶体管，电容器和检测节点。晶体管与电容器耦合，检测节点位于晶体管和电容器之间。判断模块耦合到每个检测节点。判断模块根据检测节点的电压电平生成判断。因此，形成了瞬态电压检测电路。电子系统可以根据判断选择性地执行保护动作。

23. 发明授权

US07554159B2 Electrostatic discharge protection device and method of manufacturing the same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US07554159B2
公开(公告)日：2009-06-30
申请号：US11045300
申请日：2005-01-31
申请人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang , Jeng-Jie Peng
发明人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang , Jeng-Jie Peng
IPC分类号： H01L23/62
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.
摘要翻译：一种静电放电保护装置，包括第一掺杂剂型的半导体衬底，形成在衬底中的至少一个第二掺杂剂型的源极/漏极对，其中源极/漏极对被分离以在其间限定沟道区域，限定在源极/漏极对之间并且包括沟道区域的至少一部分的第一掺杂剂类型的掺杂区域，形成在衬底上的栅极电介质层以及形成在栅极介电层上方和沟道区域上方的栅极。

24. 发明授权

US07253453B2 Charge-device model electrostatic discharge protection using active device for CMOS circuits 有权
标题翻译：使用有源器件的CMOS电路的充电器件型静电放电保护
公开(公告)号：US07253453B2
公开(公告)日：2007-08-07
申请号：US10442261
申请日：2003-05-21
申请人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang
IPC分类号： H01L21/336
CPC分类号： H01L27/0266
摘要： An integrated circuit for providing electrostatic discharge protection that includes a contact pad, a CMOS device including a transistor having a substrate, and a CDM clamp for providing electrostatic discharge protection coupled between the contact pad and the CMOS device, the CDM clamp including at least one active device, wherein the CDM clamp conducts electrostatic charges accumulated in the substrate of the transistor to the contact pad and wherein the CMOS device is coupled between a high voltage line and a low voltage line.
摘要翻译：一种用于提供静电放电保护的集成电路，其包括接触焊盘，包括具有衬底的晶体管的CMOS器件和用于提供耦合在所述接触焊盘和所述CMOS器件之间的静电放电保护的CDM钳位，所述CDM夹具包括至少一个有源器件，其中CDM钳位将积聚在晶体管的衬底中的静电电荷传导到接触焊盘，并且其中CMOS器件耦合在高压线和低电压线之间。

25. 发明授权

US07092227B2 Electrostatic discharge protection circuit with active device 有权
标题翻译：带有源器件的静电放电保护电路
公开(公告)号：US07092227B2
公开(公告)日：2006-08-15
申请号：US10230287
申请日：2002-08-29
申请人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang
发明人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang
IPC分类号： H02H9/00 , H02H3/22 , H01L27/01
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection circuit includes a first terminal, a second terminal, an electrostatic discharge device coupled between the first and second terminals, and an active device coupled to the electrostatic discharge device and controlling an electrostatic current through the electrostatic discharge device. The electrostatic discharge device includes at least one of an SCR, an FOD, an active device, a BJT, and an MOS device.
摘要翻译：静电放电保护电路包括第一端子，第二端子，耦合在第一和第二端子之间的静电放电装置，以及耦合到静电放电装置的有源装置，并且控制通过静电放电装置的静电电流。静电放电装置包括SCR，FOD，有源器件，BJT和MOS器件中的至少一个。

26. 发明申请

US20050219780A1 Electrostatic discharge protection device and method using depletion switch 审中-公开
标题翻译：静电放电保护装置及使用耗尽开关的方法
公开(公告)号：US20050219780A1
公开(公告)日：2005-10-06
申请号：US11137173
申请日：2005-05-25
申请人： Chyh-Yih Chang , Hsin-Chin Jiang , Ming-Dou Ker
发明人： Chyh-Yih Chang , Hsin-Chin Jiang , Ming-Dou Ker
IPC分类号： H01L23/58 , H01L27/02 , H02H9/00
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device for electrostatic discharge protection that includes a semiconductor substrate, a lightly doped region of a first dopant type formed in the substrate, a first diffusion region of the first dopant type formed at least partially in the lightly doped region, a second diffusion region of the first dopant type formed at least partially in the lightly doped region and spaced apart from the first diffusion region, a resistive path defined by the lightly doped region, the first and the second diffusion regions, and a third diffusion region of a second dopant type formed in the lightly doped region, and disposed between and spaced apart from the first and the second diffusion regions, wherein the third diffusion region keeps the resistive path at a low resistive state until a normal operation period occurs.
摘要翻译：一种用于静电放电保护的集成电路装置，包括半导体衬底，形成在衬底中的第一掺杂剂类型的轻掺杂区域，至少部分形成在轻掺杂区域中的第一掺杂剂类型的第一扩散区，第二扩散所述第一掺杂剂类型的区域至少部分地形成在所述轻掺杂区域中并且与所述第一扩散区间隔开;由所述轻掺杂区域，所述第一和第二扩散区域以及第二扩散区域的第三扩散区域限定的电阻路径掺杂剂类型形成在轻掺杂区域中，并且设置在第一和第二扩散区域之间并与第一和第二扩散区域间隔开，其中第三扩散区域将电阻路径保持在低电阻状态直到发生正常操作周期。

27. 发明申请

US20050127445A1 Electrostatic discharge protection device and method of manufacturing the same 有权
标题翻译：静电放电保护装置及其制造方法
公开(公告)号：US20050127445A1
公开(公告)日：2005-06-16
申请号：US11045300
申请日：2005-01-31
申请人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang , Jeng-Jie Peng
发明人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang , Jeng-Jie Peng
IPC分类号： H01L21/336 , H01L21/8234 , H01L23/62 , H01L27/01 , H01L27/02 , H01L31/0392 , H02H9/00
CPC分类号： H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.
摘要翻译：一种静电放电保护装置，包括第一掺杂剂型的半导体衬底，形成在衬底中的至少一个第二掺杂剂型的源极/漏极对，其中源极/漏极对被分离以在其间限定沟道区域，限定在源极/漏极对之间并且包括沟道区域的至少一部分的第一掺杂剂类型的掺杂区域，形成在衬底上的栅极电介质层以及形成在栅极介电层上方和沟道区域上方的栅极。

28. 发明授权

US06882009B2 Electrostatic discharge protection device and method of manufacturing the same 有权
公开(公告)号：US06882009B2
公开(公告)日：2005-04-19
申请号：US10230055
申请日：2002-08-29
申请人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang , Jeng-Jie Peng
发明人： Ming-Dou Ker , Tang-Kui Tseng , Hsin-Chin Jiang , Chyh-Yih Chang , Jeng-Jie Peng
IPC分类号： H01L21/265 , H01L21/8234 , H01L27/02 , H01L27/07 , H01L29/10 , H01L21/01 , H01L23/62
CPC分类号： H01L27/0277 , H01L21/26586 , H01L21/823412 , H01L21/823418 , H01L27/0716 , H01L29/1079 , H01L29/1087 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection device that includes a semiconductor substrate of a first dopant type, at least one source/drain pair of a second dopant type formed in the substrate, wherein the source/drain pair is separated to define a channel region therebetween, a lightly-doped region of the first dopant type defined between the source/drain pair and including at least a portion of the channel region, a gate dielectric layer formed over the substrate, and a gate formed over the gate dielectric layer and above the channel region.

29. 发明授权

US06633087B2 Low-capacitance bonding pad for semiconductor device 有权
标题翻译：用于半导体器件的低电容焊盘
公开(公告)号：US06633087B2
公开(公告)日：2003-10-14
申请号：US09818455
申请日：2001-03-27
申请人： Ming-Dou Ker , Hsin-Chin Jiang
发明人： Ming-Dou Ker , Hsin-Chin Jiang
IPC分类号： H01L2940
CPC分类号： H01L24/05 , H01L23/5222 , H01L24/48 , H01L2224/02122 , H01L2224/02166 , H01L2224/04042 , H01L2224/05012 , H01L2224/05093 , H01L2224/05095 , H01L2224/05096 , H01L2224/05552 , H01L2224/05554 , H01L2224/05556 , H01L2224/05567 , H01L2224/05599 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01033 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2224/45099 , H01L2924/00
摘要： A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.
摘要翻译：一种用于半导体器件的低电容焊盘。在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。接合焊盘由堆叠的金属层和金属层制成。堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。堆叠在层叠金属层中的金属层形成有小面积。堆叠在层叠金属层中的每个金属层通过插塞与相邻的金属层耦合

30. 发明授权

US06465283B1 Structure and fabrication method using latch-up implantation for improving latch-up immunity in CMOS fabrication process 有权
标题翻译：使用闩锁植入的结构和制造方法，以提高CMOS制造工艺中的闭锁抗扰度
公开(公告)号：US06465283B1
公开(公告)日：2002-10-15
申请号：US09654810
申请日：2000-09-05
申请人： Chyh-Yih Chang , Ming-Dou Ker , Hsin-Chin Jiang , Jeng-Jie Peng
发明人： Chyh-Yih Chang , Ming-Dou Ker , Hsin-Chin Jiang , Jeng-Jie Peng
IPC分类号： H01L21332
CPC分类号： H01L21/823814 , H01L21/823878 , H01L27/0921
摘要： A structure and fabrication method using latch-up implantation to improve latch-up immunity in CMOS circuit. The impedance of parasitic SCR conducting path is raised by performing an ion-implantation process on a cathode and an anode of a parasitic SCR which may induce latch-up phenomenon. Thus, the parasitic SCR is thus not easily to be conducted with a higher resistance to noise. Therefore, the latch-up immunity can be improved. In addition, the ion implantation process can be performed to achieve the objective of preventing latch-up effect without consuming more area for layout, thus greatly enhances the flexibility in circuit design.
摘要翻译：使用闭锁注入来提高CMOS电路中的闭锁抑制的结构和制造方法。通过在寄生SCR的阴极和阳极上执行离子注入工艺来提高寄生SCR导通路径的阻抗，这可能引起闩锁现象。因此，寄生SCR因此不容易以更高的抗噪声进行。因此，可以提高闩锁抗扰度。此外，可以进行离子注入工艺以实现防止闩锁效应的目的，而不消耗更多的布局面积，从而大大增强了电路设计的灵活性。

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