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21. 发明申请

US20090152652A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20090152652A1
公开(公告)日：2009-06-18
申请号：US12323770
申请日：2008-11-26
申请人： Yoshifumi NISHI , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
发明人： Yoshifumi NISHI , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译：这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。第二金属沉积在金属半导体化合物层上。通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

22. 发明授权

US07977182B2 Method of manufacturing MISFET with low contact resistance 失效
标题翻译：具有低接触电阻的MISFET的制造方法
公开(公告)号：US07977182B2
公开(公告)日：2011-07-12
申请号：US12323770
申请日：2008-11-26
申请人： Yoshifumi Nishi , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
发明人： Yoshifumi Nishi , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
IPC分类号： H01L21/8238 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/285
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译：这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。第二金属沉积在金属半导体化合物层上。通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

23. 发明授权

US07569879B2 Nonvolatile semiconductor memory device and manufacturing method thereof 失效
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US07569879B2
公开(公告)日：2009-08-04
申请号：US11699334
申请日：2007-01-30
申请人： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
发明人： Atsuhiro Kinoshita , Riichiro Shirota , Hiroshi Watanabe , Kenichi Murooka , Junji Koga
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11556 , H01L27/11568
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, plural semiconductor columns arranged in a matrix form on the substrate, plural first conductive areas zonally formed in a column direction on the substrate between the semiconductor columns and functioning as word lines, plural second conductive areas formed at tops of the semiconductor columns, respectively, plural bit lines connecting the second conductive areas in a row direction, plural channel areas respectively formed in the semiconductor columns between the first and second conductive areas and contacting the first and second conductive areas, plural third conductive areas continuously formed via first insulating films above the substrate and opposite to the channel areas in the column direction between the semiconductor columns and functioning as control gates, and plural charge accumulation areas respectively formed via second insulating films at upper portions of the channel areas at a position higher than the third conductive areas.
摘要翻译：非易失性半导体存储器件包括：半导体衬底，以矩阵形式布置在衬底上的多个半导体柱，在半导体柱之间的衬底上的列方向上分区形成的多个第一导电区域，并且用作字线，形成多个第二导电区域在半导体柱的顶部分别分别连接在行方向上的第二导电区域的多个位线，分别形成在第一和第二导电区域之间的半导体柱中并与第一和第二导电区域接触的多个沟道区域，多个第三导电通过基板上方的第一绝缘膜连续形成的区域，并且与半导体柱之间的列方向上的沟道区域相对，并且用作控制栅极，以及分别在沟道区域的上部经由第二绝缘膜形成的多个电荷累积区域位置高她比第三个导电区域。

24. 发明申请

US20060220131A1 Fin-type channel transistor and method of manufacturing the same 失效
公开(公告)号：US20060220131A1
公开(公告)日：2006-10-05
申请号：US11384269
申请日：2006-03-21
申请人： Atsuhiro Kinoshita , Junji Koga , Yukio Nakabayashi
发明人： Atsuhiro Kinoshita , Junji Koga , Yukio Nakabayashi
IPC分类号： H01L21/8234 , H01L27/12 , H01L21/336 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/088 , H01L21/823412 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41733 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/78618
摘要： It is possible to reliably implant an impurity into an impurity forming region, and to form a self-aligned silicides on the entire portion of the source and drain regions. There are provided: a first semiconductor layer of a first conductivity type in a substantially a rectangular solid shape formed on a substrate; a gate electrode formed on a pair of first side portions of the first semiconductor layer facing to each other with a gate insulating film being placed between the gate electrode and the first side portions; a second semiconductor layer of the first conductivity type connected to bottom portions of a pair of second side portions of the first semiconductor layer placed in a substantially perpendicular direction with respect to the first side portions, the second semiconductor layer extending along the substantially perpendicular direction; a first impurity region of a second conductivity type formed in the second semiconductor layer; second impurity regions formed on the pair of side portions of the first semiconductor layer and connected to the first impurity region; and a channel region formed between the second impurity regions of the first semiconductor layer.

25. 发明授权

US07479674B2 Field effect transistor 失效
标题翻译：场效应晶体管
公开(公告)号：US07479674B2
公开(公告)日：2009-01-20
申请号：US12034822
申请日：2008-02-21
申请人： Yukio Nakabayashi , Kazumi Nishinohara , Atsuhiro Kinoshita , Junji Koga
发明人： Yukio Nakabayashi , Kazumi Nishinohara , Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译：场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极，并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

26. 发明申请

US20080001224A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20080001224A1
公开(公告)日：2008-01-03
申请号：US11812609
申请日：2007-06-20
申请人： Atsuhiro Kinoshita , Junji Koga
发明人： Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6653
摘要： A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.
摘要翻译：提供了可以有效地抑制短通道效应和结漏电的半导体器件。半导体器件包括场效应晶体管。场效应晶体管包括第一导电类型的第一半导体区域，形成在栅极绝缘膜上的栅极电极以及源极和漏极电极。场效应晶体管还包括第二导电类型的第二半导体区域。场效应晶体管还包括具有比第二半导体区域的杂质浓度高的第二导电类型的第三半导体区域，并且形成在源电极和第一和第二半导体区域之间以及在漏电极和第一和第二半导体之间区域和形成在栅电极的两个侧表面上的侧壁绝缘膜。源电极和漏电极与侧壁绝缘膜分离。

27. 发明申请

US20050212055A1 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US20050212055A1
公开(公告)日：2005-09-29
申请号：US11081348
申请日：2005-03-16
申请人： Yukio Nakabayashi , Kazumi Nishinohara , Atsuhiro Kinoshita , Junji Koga
发明人： Yukio Nakabayashi , Kazumi Nishinohara , Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L29/417 , H01L21/00 , H01L21/336 , H01L29/76 , H01L29/772 , H01L29/78 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66643 , H01L29/66795 , H01L29/7839 , H01L29/78621
摘要： An field effect transistor includes a first semiconductor region, a gate electrode insulatively disposed over the first semiconductor region, source and drain electrodes between which the first semiconductor region is sandwiched, and second semiconductor regions each formed between the first semiconductor region and one of the source and drain electrodes, and having impurity concentration higher than that of the first semiconductor region, the source electrode being offset to the gate electrode in a direction in which the source electrode and the drain electrode are separated from each other with respect to a channel direction, and one of the second semiconductor regions having a thickness not more than a thickness with which the one of second semiconductor regions is completely depleted in the channel direction being in thermal equilibrium with the source electrode therewith.
摘要翻译：场效应晶体管包括第一半导体区域，绝缘地设置在第一半导体区域上的栅极电极，夹在第一半导体区域之间的源极和漏极电极以及形成在第一半导体区域和源极之一之间的第二半导体区域和漏电极，其杂质浓度高于第一半导体区域，源电极在源电极和漏电极相对于沟道方向彼此分离的方向上偏移到栅电极，并且所述第二半导体区域中的一个具有不大于所述第二半导体区域中的所述第二半导体区域在所述沟道方向上完全耗尽的厚度的厚度与所述源极电极处于热平衡。

28. 发明申请

US20050093033A1 Field effect transistor and manufacturing method thereof 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20050093033A1
公开(公告)日：2005-05-05
申请号：US10933333
申请日：2004-09-03
申请人： Atsuhiro Kinoshita , Junji Koga
发明人： Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L21/28 , H01L21/336 , H01L21/77 , H01L21/8238 , H01L21/84 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/417 , H01L29/45 , H01L29/78 , H01L29/786 , H01L29/94
CPC分类号： H01L29/785 , H01L21/84 , H01L27/1203 , H01L29/458 , H01L29/6653 , H01L29/6659 , H01L29/66643 , H01L29/66772 , H01L29/66795 , H01L29/7833 , H01L29/7839 , H01L29/78618 , H01L29/78645
摘要： A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.
摘要翻译：场效应晶体管包括形成沟道区域的第一半导体区域，绝缘地设置在第一半导体区域上方的栅电极，形成为在沟道纵向方向夹着第一半导体区域的源电极和漏电极，以及形成在第一半导体区域之间的第二半导体区域半导体区域和源极和漏极，并且具有高于第一半导体区域的杂质浓度。通道长度方向上的第二半导体区域的厚度被设定为等于或小于由杂质浓度确定的耗尽层宽度的值，使得第二半导体区域在无电压施加状态下耗尽。

29. 发明申请

US20090325357A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20090325357A1
公开(公告)日：2009-12-31
申请号：US12585034
申请日：2009-09-01
申请人： Atsuhiro Kinoshita , Junji Koga
发明人： Atsuhiro Kinoshita , Junji Koga
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L29/1045 , H01L29/1083 , H01L29/665 , H01L29/6653
摘要： A semiconductor device which can effectively suppress a short channel effect and junction leakage is provided. A semiconductor device includes a field effect transistor. The field effect transistor includes a first semiconductor region of a first conductivity type, a gate electrode formed on a gate insulating film, and source and drain electrodes. The field effect transistor also includes second semiconductor regions of a second conductivity type. The field effect transistor further includes third semiconductor regions of the second conductivity type having an impurity concentration higher than that of the second semiconductor region and formed between the source electrode and the first and second semiconductor regions and between the drain electrode and the first and second semiconductor regions, and side wall insulating films formed on both the side surfaces of the gate electrode. The source electrode and the drain electrode are separated from the side wall insulating films.
摘要翻译：提供了可以有效地抑制短通道效应和结漏电的半导体器件。半导体器件包括场效应晶体管。场效应晶体管包括第一导电类型的第一半导体区域，形成在栅极绝缘膜上的栅极电极以及源极和漏极电极。场效应晶体管还包括第二导电类型的第二半导体区域。场效应晶体管还包括具有比第二半导体区域的杂质浓度高的第二导电类型的第三半导体区域，并且形成在源电极和第一和第二半导体区域之间以及在漏电极和第一和第二半导体之间区域和形成在栅电极的两个侧表面上的侧壁绝缘膜。源电极和漏电极与侧壁绝缘膜分离。

30. 发明申请

US20080315183A1 SEMICONDUCTOR DEVICE WITH CARBON NANOTUBE CHANNEL AND MANUFACTURING METHOD THEREOF 审中-公开
标题翻译：具有碳纳米管通道的半导体器件及其制造方法
公开(公告)号：US20080315183A1
公开(公告)日：2008-12-25
申请号：US12052229
申请日：2008-03-20
申请人： Atsuhiro KINOSHITA , Yoshifumi Nishi , Ken Uchida , Junji Koga
发明人： Atsuhiro KINOSHITA , Yoshifumi Nishi , Ken Uchida , Junji Koga
IPC分类号： H01L29/12 , H01L21/336
CPC分类号： H01L51/105 , B82Y10/00 , H01L51/0048 , H01L51/0512 , H01L51/0541 , H01L51/0545
摘要： A high-performance semiconductor device having a channel region structured from a carbon nanotube (CNT) for reducing or minimizing a drain leakage current is provided. This semiconductor device includes, in addition to the CNT-formed channel region, a gate electrode formed to overlie the channel region with a gate insulation film sandwiched therebetween, and a pair of source and drain regions interposing the channel region therebetween. The source and drain regions have portions in contact with the channel region, which portions are made of a specific semiconductor material that is wider in energy band gap than the channel region.
摘要翻译：提供了一种具有由碳纳米管（CNT）构成的沟道区，用于降低或最小化漏极漏电流的高性能半导体器件。除了CNT形成的沟道区域之外，该半导体器件还包括形成为覆盖沟道区域的栅电极，其间夹有栅极绝缘膜，并且在其间插入沟道区域的一对源极和漏极区域。源极区和漏极区具有与沟道区接触的部分，这些部分由能量带隙比通道区宽的特定半导体材料制成。

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