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    • 23. 发明授权
    • Nonvolatile memory device
    • 非易失性存储器件
    • US08581226B2
    • 2013-11-12
    • US13236729
    • 2011-09-20
    • Kensuke Takahashi
    • Kensuke Takahashi
    • H01L29/06H01L27/108G11C27/00G11C11/00
    • H01L45/146G11C13/0007H01L27/2481H01L45/04H01L45/1683
    • According to one embodiment, a nonvolatile memory device includes a word line interconnect layer, a bit line interconnect layer, and a pillar. The word line interconnect layer includes a plurality of word lines extending in a first direction. The bit line interconnect layer includes a plurality of bit lines extending in a second direction. The pillar is disposed between each of the word lines and each of the bit lines. The pillar includes a current selection film and a plurality of variable resistance films stacked on the current selection film. One variable resistance film includes a metal and either oxygen or nitrogen. Remainder of the variable resistance films include the metal, either oxygen or nitrogen, and a highly electronegative substance having electronegativity higher than electronegativity of the metal. A concentration of highly electronegative substance in the remainder of the variable resistance films is different among the variable resistance films.
    • 根据一个实施例,非易失性存储器件包括字线互连层,位线互连层和柱。 字线互连层包括沿第一方向延伸的多个字线。 位线互连层包括沿第二方向延伸的多个位线。 支柱设置在每个字线和每个位线之间。 支柱包括电流选择膜和堆叠在当前选择膜上的多个可变电阻膜。 一个可变电阻膜包括金属和氧或氮。 可变电阻膜的剩余包括金属,氧或氮,以及具有高于金属的电负性的电负性的高电负性物质。 可变电阻膜的其余部分中高度负电性物质的浓度在可变电阻膜中是不同的。
    • 27. 发明授权
    • Semiconductor device and method for manufacturing same
    • 半导体装置及其制造方法
    • US07859059B2
    • 2010-12-28
    • US12375183
    • 2007-07-23
    • Kensuke Takahashi
    • Kensuke Takahashi
    • H01L29/76H01L29/94H01L31/062H01L31/119
    • H01L29/4908H01L21/28097H01L21/823835H01L21/823842H01L21/823878H01L21/84H01L21/845H01L27/1203H01L27/1211H01L29/4975H01L29/66545H01L29/66803H01L29/785
    • There is provided a semiconductor device having excellent device characteristics and reliability in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be values necessary for a low-power device. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a fully depleted MOS transistor including a first gate electrode comprising at least one type of crystalline phase selected from the group consisting of a WSi2 crystalline phase, an MoSi2 crystalline phase, an NiSi crystalline phase, and an NiSi2 crystalline phase as silicide region (1). The nMOS transistor is a fully depleted MOS transistor comprising at least one type of crystalline phase selected from the group consisting of a PtSi crystalline phase, a Pt2Si crystalline phase, an IrSi crystalline phase, an Ni2Si crystalline phase, and an Ni3Si crystalline phase as silicide region (2).
    • 提供了具有优异的器件特性和可靠性的半导体器件,其中nMOS晶体管和pMOS晶体管的Vth值被控制为低功率器件所需的值。 半导体器件包括通过使用SOI衬底形成的pMOS晶体管和nMOS晶体管。 pMOS晶体管是完全耗尽的MOS晶体管,其包括第一栅电极,其包括选自由WSi2结晶相,MoSi 2结晶相,NiSi结晶相和NiSi 2结晶相组成的组中的至少一种晶体相,作为硅化物 区域(1)。 nMOS晶体管是完全耗尽的MOS晶体管,其包括选自PtSi结晶相,Pt 2 Si结晶相,IrSi结晶相,Ni 2 Si结晶相和作为硅化物的Ni 3 Si结晶相中的至少一种结晶相 区域(2)。
    • 28. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    • 半导体器件及其制造方法
    • US20100155844A1
    • 2010-06-24
    • US12375708
    • 2007-07-25
    • Kensuke Takahashi
    • Kensuke Takahashi
    • H01L27/092H01L21/8238
    • H01L29/4908H01L21/28097H01L21/823835H01L21/823878H01L21/84H01L21/845H01L27/1203H01L27/1211H01L29/66545H01L29/66803H01L29/785
    • There is provided a semiconductor device having excellent device characteristics in which Vth values of an nMOS transistor and a pMOS transistor are controlled to be desired values. The semiconductor device includes a pMOS transistor and an nMOS transistor formed by using an SOI substrate. The pMOS transistor is a fully depleted transistor including an n-type region, a first gate electrode, a first gate insulating film, and a source/drain region, and the nMOS transistor is a fully depleted transistor including a p-type region, a second gate electrode, a second gate insulating film, and a source/drain region. The first gate electrode includes silicide region comprising an NiSi crystalline phase containing an n-type impurity, the silicide region being in contact with the first gate insulating film, and the second gate electrode includes silicide region comprising an NiSi crystalline phase containing a p-type impurity, the silicide region being in contact with the second gate insulating film.
    • 提供了具有优异的器件特性的半导体器件,其中nMOS晶体管和pMOS晶体管的Vth值被控制为期望值。 半导体器件包括通过使用SOI衬底形成的pMOS晶体管和nMOS晶体管。 pMOS晶体管是包括n型区域,第一栅极电极,第一栅极绝缘膜和源极/漏极区域的完全耗尽的晶体管,并且nMOS晶体管是包括p型区域的完全耗尽的晶体管, 第二栅极电极,第二栅极绝缘膜和源极/漏极区域。 第一栅电极包括包含含有n型杂质的NiSi晶相的硅化物区,硅化物区与第一栅极绝缘膜接触,第二栅电极包括含有包含p型的NiSi晶相的硅化物区 所述硅化物区域与所述第二栅极绝缘膜接触。