专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US5818797A Time measuring device 失效
标题翻译：时间测量装置
公开(公告)号：US5818797A
公开(公告)日：1998-10-06
申请号：US908975
申请日：1997-08-08
申请人： Takamoto Watanabe , Hirofumi Isomura
发明人： Takamoto Watanabe , Hirofumi Isomura
IPC分类号： G04F10/04 , G04F10/00 , G04F8/00 , H03B5/00
CPC分类号： G04F10/00
摘要： To provide a time measuring apparatus which is compact and capable of highly accurate measurements, on a semiconductor chip, flip-flops constituting a delayed-signal holding circuit of a first channel and flip-flops constituting a delayed-signal holding circuit of a second channel are disposed alternatingly and in a single row in a circuit region of the delayed-signal holding circuits to latch delayed signals from a pulse-circulating circuit, and flip-flops for latching the same delay signals are mutually adjacent. Due to this, distances between the pulse-circulating circuit and the respective delayed-signal holding circuits become equal, and delay signals having no deviation in delay due to difference in wiring length are supplied to the respective channels, and so uniform measurement can be performed between the respective channels.
摘要翻译：为了提供紧凑且能够高精度测量的时间测量装置，在半导体芯片上，构成第一通道的延迟信号保持电路的触发器和构成第二通道的延迟信号保持电路的触发器在延迟信号保持电路的电路区域中交替且单行地设置，以锁存来自脉冲循环电路的延迟信号，并且用于锁存相同延迟信号的触发器相互相邻。由此，脉冲循环电路和各延迟信号保持电路之间的距离变得相等，并且由于布线长度的差异而没有延迟偏差的延迟信号被提供给各个通道，因此可以进行均匀的测量在各个通道之间。

22. 发明授权

US5627397A Semiconductor acceleration sensor with source and drain regions 失效
标题翻译：具有源极和漏极区域的半导体加速度传感器
公开(公告)号：US5627397A
公开(公告)日：1997-05-06
申请号：US402949
申请日：1995-03-13
申请人： Kazuhiko Kano , Yukihiro Takeuchi , Takamoto Watanabe , Kenichi Ao , Masakazu Kanosue , Hirofumi Uenoyama , Kenichi Nara
发明人： Kazuhiko Kano , Yukihiro Takeuchi , Takamoto Watanabe , Kenichi Ao , Masakazu Kanosue , Hirofumi Uenoyama , Kenichi Nara
IPC分类号： G01P1/00 , G01P15/12 , H01L29/84 , H01L29/82
CPC分类号： G01P15/124 , G01P1/006 , Y10S73/01
摘要： A semiconductor acceleration sensor according to the present invention performs acceleration detection by means of detecting increase or decrease in electrical current flowing between fixed electrodes formed on a semiconductor substrate taking a movable section in a movable state supported on the semiconductor substrate as a gate electrode. Two transistor structures are utilized in this detection. Current between fixed electrodes in one transistor structure increases when the movable section is subjected to acceleration and is displaced. At that time, current between fixed electrodes in the other transistor structure decreases. These two transistor structures are disposed proximately. By means of this proximate disposition, fluctuations in characteristics of both transistors are reduced, and by means of acceleration detection by differential type, temperature characteristics of the two transistors can be canceled favorably.
摘要翻译：根据本发明的半导体加速度传感器通过检测形成在半导体衬底上的固定电极之间的电流的增加或减少来执行加速度检测，该半导体衬底以可移动状态支撑在作为栅电极的半导体衬底上的可移动状态。在该检测中使用两个晶体管结构。一个晶体管结构中的固定电极之间的电流在可移动部分受到加速并被移位时增加。此时，另一晶体管结构中的固定电极之间的电流降低。这两个晶体管结构靠近地设置。通过这种接近的配置，两个晶体管的特性波动减小，并且通过差分类型的加速度检测，可以有利地消除两个晶体管的温度特性。

23. 发明授权

US5541437A Acceleration sensor using MIS-like transistors 失效
标题翻译：加速传感器采用MIS类晶体管
公开(公告)号：US5541437A
公开(公告)日：1996-07-30
申请号：US404295
申请日：1995-03-14
申请人： Takamoto Watanabe , Shigeru Nonoyama , Yukihiro Takeuchi
发明人： Takamoto Watanabe , Shigeru Nonoyama , Yukihiro Takeuchi
IPC分类号： G01P15/125 , B81B3/00 , G01P15/08 , G01P15/12 , G01P15/13 , H01L29/84 , H01L29/82
CPC分类号： G01P15/131 , G01P15/124 , G01P2015/0814 , Y10S73/01
摘要： In an acceleration sensor having movable gates and a movable electrode and having a signal processing portion, the movable gates generate a differential voltage from acceleration in one direction and its output signal is fed back to the movable electrode. The balance of the movable portion is kept using an electrostatic force which cancels the acceleration acting on the movable portion, and signal detection is stabilized using closed loop control. Since signal detection is on a differential basis, acceleration can be detected in only one direction. Since a change in current is detected as a voltage difference, no carrier wave is required. Since MISFETs having movable gates are formed in pairs, there is no influence of temperature drifts. The use of a differential signal similarly cancels the influence of fluctuations of the power supply. Configuration of an acceleration sensor is thus simplified.
摘要翻译：在具有可动栅极和可动电极并具有信号处理部分的加速度传感器中，可移动栅极从一个方向的加速度产生差分电压，并将其输出信号反馈到可动电极。使用抵消作用在可动部上的加速度的静电力来保持可动部的平衡，并且使用闭环控制来稳定信号检测。由于信号检测是基于差分的，所以只能在一个方向上检测加速度。由于电流变化被检测为电压差，因此不需要载波。由于具有可动栅极的MISFET成对成形，所以不会有温度漂移的影响。差分信号的使用也可以抵消电源波动的影响。因此，加速度传感器的结构被简化。

24. 发明授权

US5525939A Recirculating delay line digital pulse generator having high control proportionality 失效
标题翻译：具有高控制比例的再循环延迟线数字脉冲发生器
公开(公告)号：US5525939A
公开(公告)日：1996-06-11
申请号：US501269
申请日：1995-07-12
申请人： Shigenori Yamauchi , Takamoto Watanabe
发明人： Shigenori Yamauchi , Takamoto Watanabe
IPC分类号： H03K3/03 , H03K5/135 , H03B5/24 , H03K3/012 , H03K3/027
CPC分类号： H03K3/0315 , H03K5/135
摘要： In a digital control pulse generator including a ring oscillator composed of multiple inversion circuits connected in a ring for circulating a pulse, a counter and selectors which turn data of a flip-flop to high when a counted value of the pulse from a terminal of the ring oscillator becomes a value corresponding to ten high order bits of control data, a pulse selector for taking out a clock of the flip-flop from the inversion circuit at the position specified by four bit control data and a delay line and logical product circuit which turn an output signal of the system to a high level for a predetermined time when the output of the flip-flop turns high, a register and adder accumulate the four low order bits of the control data every time the output signal turns high to update the data four bit data. As a result, the ring oscillator may be continuously operated and an oscillation cycle proportional to the control data may be set.
摘要翻译：在包括环形振荡器的数字控制脉冲发生器中，所述环形振荡器由连接在环中以循环脉冲的多个反相电路组成，计数器和选择器将触发器的数据值从环形振荡器成为对应于控制数据的十个高位位的值，用于在由四位控制数据指定的位置处的反相电路中取出触发器的时钟的脉冲选择器和延迟线以及逻辑积电路，当触发器的输出变为高电平时，将系统的输出信号转换到高电平达预定时间，寄存器和加法器在每当输出信号变为高电平时累积控制数据的四个低位，以更新数据四位数据。结果，可以连续地操作环形振荡器，并且可以设置与控制数据成比例的振荡周期。

25. 发明授权

US5477196A Pulse generator 失效
标题翻译：脉冲发生器
公开(公告)号：US5477196A
公开(公告)日：1995-12-19
申请号：US362648
申请日：1994-12-23
申请人： Shigenori Yamauchi , Takamoto Watanabe
发明人： Shigenori Yamauchi , Takamoto Watanabe
IPC分类号： G01R25/00 , G01R25/08 , G01R29/02 , H03K3/03 , H03K3/354 , H03K5/00 , H03K5/135 , H03K5/26 , H03L7/06 , H03L7/085 , H03B27/00 , H03L7/083 , H03L7/18
CPC分类号： H03K3/0315 , H03K5/135
摘要： In a device for encoding a pulse phase difference or controlling an oscillation frequency based on delayed signals sequentially output by a delay circuit, the encoding of a pulse phase difference or the oscillation control can be simultaneously performed using a single delay device. There is provided a frequency converter including a ring oscillator consisting of inverting circuits interconnected in the form of a ring, a pulse phase difference encoding circuit for encoding the cycle of a reference signal into a binary digital value based on a pulse output by the ring oscillator, an arithmetic circuit for multiplying or dividing the binary digital value by a predetermined value to generate control data and a digitally controlled oscillation circuit for generating a pulse signal in a cycle in accordance with the control data based on the pulse output by the ring oscillator, the ring oscillator being shared by the encoding circuit and oscillation circuit. This makes the time resolution of the encoding and oscillation circuits constant, thereby allowing accurate frequency conversion.
摘要翻译：在根据由延迟电路顺序输出的延迟信号对脉冲相位差进行编码或控制振荡频率的装置中，可以使用单个延迟装置同时进行脉冲相位差的编码或振荡控制。提供了一种变频器，包括由环形互连的反相电路构成的环形振荡器，用于基于环形振荡器输出的脉冲将参考信号的周期编码为二进制数字值的脉冲相位差编码电路，用于将二进制数字值乘以预定值以产生控制数据的运算电路和用于根据由环形振荡器输出的脉冲输出的控制数据在一个周期内产生脉冲信号的数字控制振荡电路，环形振荡器由编码电路和振荡电路共享。这使得编码和振荡电路的时间分辨率恒定，从而允许精确的频率转换。

26. 发明申请

US20120039588A1 A/D CONVERSION CIRCUIT, SIGNAL PROCESSING CIRCUIT, AND SHAKE DETECTION DEVICE 有权
标题翻译： A / D转换电路，信号处理电路和SHAKE检测装置
公开(公告)号：US20120039588A1
公开(公告)日：2012-02-16
申请号：US13277602
申请日：2011-10-20
申请人： Yasunari Harada , Takamoto Watanabe
发明人： Yasunari Harada , Takamoto Watanabe
IPC分类号： G03B17/00 , H03M3/04
CPC分类号： H04N5/23248 , G03B5/00 , G03B2205/0007 , H03M1/0663 , H03M1/123 , H03M1/502 , H04N5/23258 , H04N5/2328 , H04N5/361 , H04N5/378
摘要： The A/D conversion circuit may include A/D conversion units each of which converts input analog signals into digital signals, a switch unit that receives a first and second analog signals among the analog signals, the switch unit alternately switching output destinations of the first and second analog signals input in the same period to the A/D conversion units in each sampling cycle of the A/D conversion units; and an arithmetic unit that performs a differential operation between a result of addition of the digital signals output from the A/D conversion units to which the first analog signal is input and a result of addition of the digital signals output from the A/D conversion units which the second analog signal is input, the arithmetic unit outputting a third digital signal corresponding to a result of the differential operation.
摘要翻译： A / D转换电路可以包括将输入模拟信号转换为数字信号的A / D转换单元，接收模拟信号中的第一和第二模拟信号的开关单元，开关单元交替地切换第一以及在A / D转换单元的每个采样周期中在相同周期中输入到A / D转换单元的第二模拟信号; 以及算术单元，其执行从输入第一模拟信号的A / D转换单元输出的数字信号的相加结果与从A / D转换器输出的数字信号的相加结果之间的差分运算输入第二模拟信号的单元，运算单元输出与差分运算结果对应的第三数字信号。

27. 发明申请

US20100073542A1 IMAGE SENSOR AND CONTROL METHOD OF THE IMAGE SENSOR 审中-公开
标题翻译：图像传感器和图像传感器的控制方法
公开(公告)号：US20100073542A1
公开(公告)日：2010-03-25
申请号：US12627780
申请日：2009-11-30
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H04N5/335
CPC分类号： H04N5/37455
摘要： An image sensor has plural array blocks B1 to B20 arranged in a two dimensional (2D) arrangement. Each array block has a sub array and a corresponding analogue to digital (A/D) converter for performing an A/D conversion of light signals (or detection signals) output from the sub array. The sub array has plural picture element cells arranged in a 2D arrangement. Each A/D converter has a pulse delay circuit having delay units of plural stages connected in series. Each delay unit delays an input pulse by a delay time corresponding to a level of the light signals received from the sub array. A pulse delay type A/D converter is used as the A/D converter, which outputs the number of the delay units as an A/D conversion data item through which the input pulse passes for a measurement time period.
摘要翻译：图像传感器具有以二维（2D）布置排列的多个阵列块B1至B20。每个阵列块具有子阵列和相应的模数（A / D）转换器，用于执行从子阵列输出的光信号（或检测信号）的A / D转换。子阵列具有以2D排列布置的多个像素单元。每个A / D转换器具有串联连接的多级延迟单元的脉冲延迟电路。每个延迟单元将输入脉冲延迟与从子阵列接收的光信号的电平相对应的延迟时间。使用脉冲延迟型A / D转换器作为A / D转换器，其输出延迟单元的数量作为输入脉冲经过测量时间段的A / D转换数据项。

28. 发明授权

US07525878B2 Time measuring circuit with pulse delay circuit 有权
标题翻译：具有脉冲延迟电路的时间测量电路
公开(公告)号：US07525878B2
公开(公告)日：2009-04-28
申请号：US11807712
申请日：2007-05-30
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： G04F10/00 , H03H11/01
CPC分类号： G04F10/00
摘要： In a time measuring circuit, a pulse delay circuit is provided with a plurality of delay units. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on a level of a first drive voltage being input to each of the plurality of delay units. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate, as time measurement data, digital data based on the obtained number. A first setting unit is configured to variably set the level of the first drive voltage being input to each of the plurality of delay units.
摘要翻译：在时间测量电路中，脉冲延迟电路具有多个延迟单元。脉冲延迟电路被配置为在脉冲信号被多个延迟单元延迟的同时通过多个延迟单元传送脉冲信号。多个延迟单元中的每一个的延迟时间取决于输入到多个延迟单元中的每一个的第一驱动电压的电平。发电电路被配置为获得脉冲信号在预定时间段内通过的多个延迟单元，作为时间测量数据生成基于获得的数量的数字数据。第一设置单元被配置为可变地设置输入到多个延迟单元中的每一个的第一驱动电压的电平。

29. 发明申请

US20070268172A1 Analog-to-digital converter with pulse delay circuit 有权
标题翻译：具有脉冲延迟电路的模数转换器
公开(公告)号：US20070268172A1
公开(公告)日：2007-11-22
申请号：US11804946
申请日：2007-05-21
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H03M1/12
CPC分类号： H03M1/502 , H03M1/14 , H03M1/60
摘要： In a semiconductor-integrated A/D converter, a pulse delay circuit is provided with a plurality of delay units. The plurality of delay units each includes at least one logic gate and operates based on a level of an input signal. The pulse delay circuit is configured to transfer a pulse signal through the plurality of delay units while the pulse signal is delayed by the plurality of delay units. A delay time of each of the plurality of delay units depends on the level of the input signal. The at least one logic gate is composed of at least one first transistor. The at least one first transistor has a first threshold voltage. A generating circuit is configured to obtain a number of the delay units through which the pulse signal has passed within a predetermined period to generate digital data based on the obtained number. The generating circuit is composed of at least one second transistor. The at least one second transistor has a second threshold voltage. The first threshold voltage of the at least one first transistor is lower than the second threshold voltage of the at least one second transistor.
摘要翻译：在半导体集成A / D转换器中，脉冲延迟电路具有多个延迟单元。多个延迟单元各自包括至少一个逻辑门并且基于输入信号的电平进行操作。脉冲延迟电路被配置为在脉冲信号被多个延迟单元延迟的同时通过多个延迟单元传送脉冲信号。多个延迟单元中的每一个的延迟时间取决于输入信号的电平。至少一个逻辑门由至少一个第一晶体管组成。所述至少一个第一晶体管具有第一阈值电压。发电电路被配置为获得脉冲信号在预定时间段内通过的多个延迟单元，以基于获得的数量生成数字数据。发电电路由至少一个第二晶体管构成。所述至少一个第二晶体管具有第二阈值电压。所述至少一个第一晶体管的第一阈值电压低于所述至少一个第二晶体管的第二阈值电压。

30. 发明申请

US20060290555A1 A/D converter that is implemented using only digital circuit components and digital signal processing 有权
标题翻译：仅使用数字电路元件和数字信号处理实现的A / D转换器
公开(公告)号：US20060290555A1
公开(公告)日：2006-12-28
申请号：US11442127
申请日：2006-05-30
申请人： Takamoto Watanabe
发明人： Takamoto Watanabe
IPC分类号： H03M1/12
CPC分类号： H03M1/0612 , H03M1/145 , H03M1/207 , H03M1/502 , H03M1/60
摘要： A TAD (time analog/digital) type of A/D converter has plural series-connected delay units each producing a delay in accordance with the level of a converter input voltage, with a first-stage delay unit receiving a pulse signal at commencement of each A/D conversion sampling interval, and a latch/encoder circuit detecting the total number of delay units traversed by the pulse signal by the end of the sampling interval, to obtain a numeric value expressing the input voltage level. To ensure uniformity of the delays of the delay units, these are formed using transistors of larger size than transistors of other circuits such as the latch/encoder circuit.
摘要翻译： A / D转换器的TAD（时间模拟/数字）型具有多个串联连接的延迟单元，每个延迟单元根据转换器输入电压的电平产生延迟，第一级延迟单元在开始时接收脉冲信号每个A / D转换采样间隔，以及锁存/编码器电路，检测由采样间隔结束时由脉冲信号穿过的延迟单元的总数，以获得表示输入电压电平的数值。为了确保延迟单元的延迟的均匀性，它们使用比其他电路（例如锁存/编码器电路）的晶体管更大尺寸的晶体管来形成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式