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21. 发明申请

US20210057231A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH REDUCED TRENCH DISTORTIONS 有权
公开(公告)号：US20210057231A1
公开(公告)日：2021-02-25
申请号：US17080248
申请日：2020-10-26
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yung-Sung Yen , Chung-Ju Lee , Chun-Kuang Chen , Chia-Tien Wu , Ta-Ching Yu , Kuei-Shun Chen , Ru-Gun Liu , Shau-Lin Shue , Tsai-Sheng Gau , Yung-Hsu Wu
IPC分类号： H01L21/311 , H01L21/033 , H01L21/3213 , H01L21/768
摘要： A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

22. 发明授权

US09946827B2 Method and structure for mandrel and spacer patterning 有权
公开(公告)号：US09946827B2
公开(公告)日：2018-04-17
申请号：US14801383
申请日：2015-07-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Chung-Ming Wang , Chih-Hsiung Peng , Chi-Kang Chang , Kuei-Shun Chen , Shih-Chi Fu
IPC分类号： G06F17/50 , H01L27/088 , H01L29/06 , H01L21/8234 , H01L27/02
CPC分类号： G06F17/5068 , G06F2217/02 , H01L21/823431 , H01L27/0207 , H01L27/0886 , H01L29/0653
摘要： A method includes receiving an integrated circuit design layout that includes first and second layout blocks separated by a first space. The first and second layout blocks include, respectively, first and second line patterns oriented lengthwise in a first direction. The method further includes adding a dummy pattern to the first space, which connects the first and second line patterns. The method further includes outputting a mandrel pattern layout and a cut pattern layout in a computer-readable format. The mandrel pattern layout includes the first and second line patterns and the dummy pattern. The cut pattern layout includes a pattern corresponding to the first space. In embodiments, the method further includes manufacturing a first mask with the mandrel pattern layout and manufacturing a second mask with the cut pattern layout. In embodiments, the method further includes patterning a substrate with the first mask and the second mask.

23. 发明授权

US09793268B2 Method and structure for gap filling improvement 有权
公开(公告)号：US09793268B2
公开(公告)日：2017-10-17
申请号：US14163843
申请日：2014-01-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ying-Hao Su , Yu-Chung Su , Yu-Lun Liu , Chi-Kang Chang , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/02 , H01L21/027 , H01L29/66 , H01L21/768
CPC分类号： H01L27/0886 , H01L21/02118 , H01L21/02282 , H01L21/02299 , H01L21/02318 , H01L21/0276 , H01L21/76837 , H01L21/823431 , H01L21/823437 , H01L29/66795
摘要： The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.

24. 发明申请

US20170062222A1 Method for Integrated Circuit Patterning 有权
标题翻译：集成电路图案化方法
公开(公告)号：US20170062222A1
公开(公告)日：2017-03-02
申请号：US14841173
申请日：2015-08-31
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Tsung-Lin Yang , Hua Feng Chen , Kuei-Shun Chen , Min-Yann Hsieh , Po-Hsueh Li , Shih-Chi Fu , Yuan-Hsiang Lung , Yan-Tso Tsai
IPC分类号： H01L21/265 , H01L21/31 , H01L21/311 , H01L21/306 , H01L21/308 , H01L21/266
CPC分类号： H01L21/26586 , H01L21/0332 , H01L21/0337 , H01L21/2658 , H01L21/266 , H01L21/302 , H01L21/30608 , H01L21/308 , H01L21/3081 , H01L21/3085 , H01L21/3086 , H01L21/31 , H01L21/31111 , H01L21/32134 , H01L21/32155
摘要： A method of patterning a substrate includes forming a hard mask layer over the substrate; forming a first material layer over the hard mask layer; and forming a trench in the first material layer. The method further includes treating the hard mask layer with an ion beam through the trench. An etching rate of a treated portion of the hard mask layer reduces with respect to an etching process while an etching rate of untreated portions of the hard mask layer remains substantially unchanged with respect to the etching process. After the treating of the hard mask layer, the method further includes removing the first material layer and removing the untreated portions of the hard mask layer with the etching process, thereby forming a hard mask over the substrate. The method further includes etching the substrate with the hard mask as an etch mask.
摘要翻译：图案化衬底的方法包括在衬底上形成硬掩模层; 在所述硬掩模层上形成第一材料层; 以及在所述第一材料层中形成沟槽。该方法还包括用离子束通过沟槽处理硬掩模层。相对于蚀刻工艺，硬掩模层的处理部分的蚀刻速率降低，而硬掩模层的未处理部分的蚀刻速率在蚀刻过程中基本保持不变。在硬掩模层的处理之后，该方法还包括通过蚀刻工艺去除第一材料层和去除硬掩模层的未处理部分，从而在衬底上形成硬掩模。该方法还包括用硬掩模作为蚀刻掩模蚀刻衬底。

25. 发明授权

US09466528B2 Method of making a structure 有权
标题翻译：制作结构的方法
公开(公告)号：US09466528B2
公开(公告)日：2016-10-11
申请号：US14507101
申请日：2014-10-06
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Chu Liu , Yi-Shien Mor , Kuei-Shun Chen , Yu Lun Liu , Han-Hsun Chang , Shiao-Chian Yeh
IPC分类号： H01L21/768 , H01L21/3213 , H01L27/06
CPC分类号： H01L21/76879 , H01L21/32139 , H01L21/76802 , H01L21/76885 , H01L27/0629 , H01L2924/0002
摘要： A method of making a structure includes forming a first supporting member over a substrate, the first supporting member comprising a first material and having a first width defined along a reference plane. The method further includes forming a second supporting member over the substrate, the second supporting member having a second width defined along the reference plane, and the first supporting member and the second supporting member being separated by a gap region. The first width is at least 10 times the second width, and a gap width of the gap region being from 5 to 30 times the second width.
摘要翻译：制造结构的方法包括在基板上形成第一支撑构件，第一支撑构件包括第一材料并具有沿参考平面限定的第一宽度。该方法还包括在衬底上形成第二支撑构件，第二支撑构件具有沿着参考平面限定的第二宽度，第一支撑构件和第二支撑构件由间隙区域分开。第一宽度为第二宽度的至少10倍，间隙区域的间隙宽度为第二宽度的5至30倍。

26. 发明授权

US09431513B2 Dummy gate structure and methods thereof 有权
标题翻译：虚拟门结构及其方法
公开(公告)号：US09431513B2
公开(公告)日：2016-08-30
申请号：US14499949
申请日：2014-09-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chia-Chu Liu , Kuei-Shun Chen , Chiang Mu-Chi , Chao-Cheng Chen
IPC分类号： H01L29/66 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/823431 , H01L21/823437 , H01L21/823481 , H01L29/0649 , H01L29/0847 , H01L29/66795 , H01L29/785 , H01L29/7856
摘要： A structure and method for implementation of dummy gate structures within multi-gate device structures includes a semiconductor device including an isolation region that separates a first and second active region. The first active region is adjacent to a first side of the isolation region and the second active region is adjacent to a second side of the isolation region. A device including a source, a drain, and a gate is formed within the first active region. One of the source and drain regions are disposed adjacent to the isolation region. A dummy gate is formed at least partially over the isolation region and adjacent to the one of the source and drain regions. In various examples, the gate includes a first dielectric layer having a first thickness and the dummy gate includes a second dielectric layer having a second thickness greater than the first thickness.
摘要翻译：用于在多栅极器件结构内实现伪栅极结构的结构和方法包括：半导体器件，其包括分离第一和第二有源区的隔离区。第一有源区域与隔离区域的第一侧相邻，第二有源区域与隔离区域的第二侧相邻。在第一有源区内形成包括源极，漏极和栅极的器件。源区和漏区之一被设置在隔离区附近。至少部分地在隔离区域上形成虚拟栅极，并且与源区域和漏极区域中的一个相邻。在各种示例中，栅极包括具有第一厚度的第一介电层，并且虚设栅极包括具有大于第一厚度的第二厚度的第二介电层。

27. 发明授权

US09274414B2 Method for making a lithography mask 有权
标题翻译：光刻掩模的制造方法
公开(公告)号：US09274414B2
公开(公告)日：2016-03-01
申请号：US14558842
申请日：2014-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Chie-Chieh Lin
IPC分类号： G03F1/38 , G03F1/00
CPC分类号： G03F1/38 , G03F1/00 , G03F7/70433
摘要： A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
摘要翻译：描述制造掩模的方法。该方法包括接收接收具有包括第一特征的第一图案层并且具有包括第二特征的第二图案层的集成电路（IC）设计布局，其中当形成第一图案层和第二图案层时，第一图案层和第二图案层在空间上相关基板，使得第一和第二特征在第一特征的第一边缘和第二特征的第二边缘之间隔开第一距离，通过基于第一距离调整第一特征的尺寸来修改IC设计布局，以及从用于掩模制作的修改的IC设计布局生成带出数据。该方法还包括将逻辑运算（LOP）应用于IC设计布局。

28. 发明申请

US20150214226A1 METHOD AND STRUCTURE FOR GAP FILLING IMPROVEMENT 有权
标题翻译： GAP填充改进方法与结构
公开(公告)号：US20150214226A1
公开(公告)日：2015-07-30
申请号：US14163843
申请日：2014-01-24
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Ying-Hao SU , Yu-Chung Su , Yu-Lun Liu , Chi-Kang Chang , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L27/088 , H01L21/033 , H01L21/027 , H01L21/8234 , H01L21/02
CPC分类号： H01L27/0886 , H01L21/02118 , H01L21/02282 , H01L21/02299 , H01L21/02318 , H01L21/0276 , H01L21/76837 , H01L21/823431 , H01L21/823437 , H01L29/66795
摘要： The present disclosure provides a method for forming a semiconductor structure. The method includes providing a substrate including a plurality of fin structures on the substrate; coating a first solution on the substrate to form a first dielectric layer; and coating a second solution on the first dielectric layer to form a second dielectric layer to cover the fin structures. The first solution has a first viscosity. The second solution has a second viscosity. In some embodiments, the second viscosity is greater than the first viscosity.
摘要翻译：本公开提供了一种用于形成半导体结构的方法。该方法包括在衬底上提供包括多个翅片结构的衬底; 在所述基板上涂覆第一溶液以形成第一介电层; 以及在所述第一介电层上涂覆第二溶液以形成覆盖所述翅片结构的第二介电层。第一溶液具有第一粘度。第二溶液具有第二粘度。在一些实施方案中，第二粘度大于第一粘度。

29. 发明申请

US20150086910A1 METHOD FOR MAKING A LITHOGRAPHY MASK 有权
标题翻译：制作光刻面膜的方法
公开(公告)号：US20150086910A1
公开(公告)日：2015-03-26
申请号：US14558842
申请日：2014-12-03
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Lun Liu , Chia-Chu Liu , Kuei-Shun Chen , Chung-Ming Wang , Chie-Chieh Lin
IPC分类号： G03F1/38
CPC分类号： G03F1/38 , G03F1/00 , G03F7/70433
摘要： A method of fabricating a mask is described. The method includes receiving receiving an integrated circuit (IC) design layout that has a first pattern layer including a first feature and has a second pattern layer including a second feature, wherein the first pattern layer and the second pattern layer are spatially related when formed in a substrate such that the first and second features are spaced a first distance between a first edge of the first feature and a second edge of the second feature, modifying the IC design layout by adjusting a dimension of the first feature based on the first distance, and generating a tape-out data from the modified IC design layout for mask making. The method further includes applying a logic operation (LOP) to the IC design layout.
摘要翻译：描述制造掩模的方法。该方法包括接收接收具有包括第一特征的第一图案层并且具有包括第二特征的第二图案层的集成电路（IC）设计布局，其中当形成第一图案层和第二图案层时，第一图案层和第二图案层在空间上相关基板，使得第一和第二特征在第一特征的第一边缘和第二特征的第二边缘之间隔开第一距离，通过基于第一距离调整第一特征的尺寸来修改IC设计布局，以及从用于掩模制作的修改的IC设计布局生成带出数据。该方法还包括将逻辑运算（LOP）应用于IC设计布局。

30. 发明申请

US20140120729A1 METHOD FOR REMOVING A PATTERNED HARD MASK LAYER 审中-公开
标题翻译：用于去除图案硬掩模层的方法
公开(公告)号：US20140120729A1
公开(公告)日：2014-05-01
申请号：US13666268
申请日：2012-11-01
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Yu-Lun Liu , Ying-Hao Su , Chia-Chu Liu , Kuei-Shun Chen
IPC分类号： H01L21/308 , G06F17/50
CPC分类号： G06F17/50 , H01L21/31111 , H01L21/31116 , H01L21/31144 , H01L21/32139
摘要： The present disclosure provides embodiments of a method that includes providing a substrate having a patterned material layer and a patterned hard mask layer disposed on the patterned material layer, wherein the patterned material layer includes a material feature having a first dimension and the patterned hard mask layer includes a hard mask feature covering the material feature. The method also includes forming, on the substrate and the hard mask feature, a patterned resist layer with an opening that exposes the hard mask feature and has a second dimension as a function of the first dimension; etching back the resist film; and removing the patterned hard mask layer.
摘要翻译：本公开提供了一种方法的实施例，其包括提供具有图案化材料层和设置在图案化材料层上的图案化硬掩模层的衬底，其中图案化材料层包括具有第一尺寸的材料特征和图案化硬掩模层包括覆盖材料特征的硬掩模特征。该方法还包括在衬底和硬掩模特征上形成具有暴露硬掩模特征并具有作为第一尺寸的函数的第二尺寸的开口的图案化抗蚀剂层; 蚀刻抗蚀剂膜; 并去除图案化的硬掩模层。

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