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21. 发明授权

US07227225B2 Semiconductor device having a vertical MOS trench gate structure 失效
标题翻译：具有垂直MOS沟槽栅极结构的半导体器件
公开(公告)号：US07227225B2
公开(公告)日：2007-06-05
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

22. 发明申请

US20050001264A1 Semiconductor device having verical MOS gate structure and method of manufacturing the same 失效
标题翻译：具有真正的MOS栅极结构的半导体器件及其制造方法
公开(公告)号：US20050001264A1
公开(公告)日：2005-01-06
申请号：US10829173
申请日：2004-04-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/78 , H01L21/3205 , H01L21/336 , H01L29/08 , H01L29/10 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/76
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/407 , H01L29/41741 , H01L29/4236 , H01L29/42368 , H01L29/4238 , H01L29/4933
摘要： A second semiconductor region is formed on a first semiconductor region. A third semiconductor region is formed on a part of the second semiconductor region. A trench ranges from a surface of the third semiconductor region to the third semiconductor region and the second semiconductor region. The trench penetrates the third semiconductor region, and the depth of the trench is shorter than that of a deepest bottom portion of the second semiconductor region, and the second semiconductor region does not exist under a bottom surface of the trench. A gate insulating film is formed on facing side surfaces of the trench. First and second gate electrodes are formed on the gate insulating film. The first and second gate electrodes are separated from each other. The conductive material is formed between the first and second gate electrodes on the side surfaces of the trench, with an insulating film intervened therebetween.
摘要翻译：在第一半导体区域上形成第二半导体区域。在第二半导体区域的一部分上形成第三半导体区域。沟槽的范围从第三半导体区域的表面到第三半导体区域和第二半导体区域。沟槽穿透第三半导体区域，并且沟槽的深度比第二半导体区域的最深底部的深度短，并且第二半导体区域不存在于沟槽的底表面之下。栅极绝缘膜形成在沟槽的相对的侧表面上。在栅极绝缘膜上形成第一和第二栅电极。第一和第二栅电极彼此分离。导电材料形成在沟槽的侧表面上的第一和第二栅电极之间，绝缘膜介于其间。

23. 发明授权

US07061047B2 Semiconductor device having trench gate structure and manufacturing method thereof 有权
公开(公告)号：US07061047B2
公开(公告)日：2006-06-13
申请号：US10682111
申请日：2003-10-10
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/772
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/267 , H01L29/42368 , H01L29/4933
摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.

24. 发明申请

US20060138535A1 Semiconductor device having trench gate structure and manufacturing method thereof 审中-公开
标题翻译：具有沟槽栅极结构的半导体器件及其制造方法
公开(公告)号：US20060138535A1
公开(公告)日：2006-06-29
申请号：US11362150
申请日：2006-02-27
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/267 , H01L29/42368 , H01L29/4933
摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.
摘要翻译：垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低比第一个高峰。基于第一峰确定阈值电压，并且基于第二峰确定剂量。

25. 发明申请

US20050287744A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20050287744A1
公开(公告)日：2005-12-29
申请号：US11157908
申请日：2005-06-22
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/336 , H01L29/06 , H01L29/76 , H01L29/78 , H01L29/872 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/7806 , H01L29/872
摘要： A semiconductor device has a plurality of pillars formed by filling a poly-silicon via an insulating layer in a plurality of trenches arranged substantially in parallel at certain intervals, n+-semiconductor regions and p+-semiconductor regions which are formed between partial pillars among the plurality of pillars and alternately formed along a direction where the pillars extend, n−-semiconductor regions arranged between the other partial neighboring pillars among the plurality of pillars and a first metal layer which makes a schottky contact on an upper face of the n−-semiconductor regions.
摘要翻译：半导体器件具有通过多个沟槽中的绝缘层填充多晶硅形成的多个柱，所述多个沟槽基本上以一定间隔平行设置，n + + - 半导体区域和p + 在多个柱之间的部分柱之间形成并且沿着柱延伸的方向交替形成的半导体区域，其间布置在其中的相邻部分相邻柱之间的半导体区域多个柱状物以及在第n个半导体区域的上表面上形成肖特基接触的第一金属层。

26. 发明申请

US20050029586A1 Semiconductor device having trench gate structure and manufacturing method thereof 有权
标题翻译：具有沟槽栅极结构的半导体器件及其制造方法
公开(公告)号：US20050029586A1
公开(公告)日：2005-02-10
申请号：US10682111
申请日：2003-10-10
申请人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
发明人： Syotaro Ono , Yusuke Kawaguchi , Akio Nakagawa
IPC分类号： H01L21/336 , H01L29/08 , H01L29/267 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/94
CPC分类号： H01L29/7813 , H01L29/0847 , H01L29/0878 , H01L29/267 , H01L29/42368 , H01L29/4933
摘要： A vertical MOSFET includes a base region formed on a drain region and a source region formed in the base region. A trench is formed to extend from the surface of the source region and penetrate the source region and has depth to reach a portion near the drain region. A gate insulating film is formed on the side walls and bottom portion of the trench and the gate electrode is formed in the trench. The impurity concentration profile of the base region has a first peak in a portion near the interface between the source region and the base region and a second peak which is formed in a portion near the interface between the base region and the drain region and is lower than the first peak. The threshold voltage is determined based on the first peak and the dose amount is determined based on the second peak.
摘要翻译：垂直MOSFET包括形成在漏极区域上的基极区域和形成在基极区域中的源极区域。沟槽形成为从源极区域的表面延伸并且穿透源极区域并且具有深度以到达漏极区域附近的部分。在沟槽的侧壁和底部形成栅极绝缘膜，并且在沟槽中形成栅电极。基极区域的杂质浓度分布在源极区域和基极区域之间的界面附近的部分具有第一峰值，第二峰值形成在基极区域和漏极区域之间的界面附近的部分，并且较低比第一个高峰。基于第一峰确定阈值电压，并且基于第二峰确定剂量。

27. 发明授权

US06818945B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06818945B2
公开(公告)日：2004-11-16
申请号：US10404141
申请日：2003-04-02
申请人： Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
发明人： Yusuke Kawaguchi , Syotaro Ono , Akio Nakagawa
IPC分类号： H01L2972
CPC分类号： H01L29/7813 , H01L29/1095 , H01L29/402 , H01L29/407 , H01L29/41741
摘要： A semiconductor device according to one embodiment of the present invention includes: a semiconductor substrate of a first conductive type; a semiconductor layer of the first conductive type formed on the semiconductor substrate; a base layer of a second conductive type formed on the semiconductor layer; a plurality of columns of stripe trenches formed at predetermined intervals from a surface of the base layer by a predetermined depth; insulating films formed on side surfaces and bottoms of the trenches, respectively; source layers of the first conductive type formed on surface layer portions of the base layer between the trenches, respectively; stripe contact layers of the second conductive type formed each at centers of the surface layer portions of the base layer between the trenches, respectively; a gate electrode formed in every other trench among the plurality of columns of trenches; source electrodes formed in the trenches other than the trenches in which the gate electrodes are formed and on the source layers and the contact layers, respectively; and a drain electrode formed on a rear surface of the semiconductor substrate.
摘要翻译：根据本发明的一个实施例的半导体器件包括：第一导电类型的半导体衬底; 形成在所述半导体衬底上的所述第一导电类型的半导体层; 形成在所述半导体层上的第二导电类型的基底层; 多个柱状的条形槽，以预定的距离从基底层的表面形成预定的深度; 分别形成在沟槽的侧表面和底部的绝缘膜; 分别形成在沟槽之间的基底层的表层部分上的第一导电类型的源极层; 分别在沟槽之间的基底层的表层部分的中心分别形成第二导电类型的条状接触层; 形成在所述多个沟槽列之间的每隔一个沟槽中的栅电极; 源极电极分别形成在不同于其中形成栅电极的沟槽之外的沟槽中，并分别在源极层和接触层上形成; 以及形成在所述半导体衬底的后表面上的漏电极。

28. 发明申请

US20070194375A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20070194375A1
公开(公告)日：2007-08-23
申请号：US11674337
申请日：2007-02-13
申请人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
发明人： Yusuke Kawaguchi , Yoshihiro Yamaguchi , Syotaro Ono , Miwako Akiyama
IPC分类号： H01L29/94
CPC分类号： H01L29/7811 , H01L29/0615 , H01L29/0634 , H01L29/1095 , H01L29/402 , H01L29/41741 , H01L29/41766 , H01L29/7813
摘要： This semiconductor device comprises a first semiconductor layer of a first conductivity type, an epitaxial layer of a first conductivity type formed in the surface on the first semiconductor layer, and a base layer of a second conductivity type formed on the surface of the epitaxial layer. Column layers of a second conductivity type are repeatedly formed in the epitaxial layer under the base layer at a certain interval. Trenches are formed so as to penetrate the base layer to reach the epitaxial layer; and gate electrodes are formed in the trenches via a gate insulation film. A termination layer of a second conductivity type is formed on the epitaxial layer at an end region at the perimeter of the base layer. The termination layer is formed to have a junction depth larger than that of the base layer.
摘要翻译：该半导体器件包括形成在第一半导体层表面上的第一导电类型的第一半导体层，第一导电类型的外延层和形成在外延层的表面上的第二导电类型的基极层。第二导电类型的列层以一定间隔在基底层下的外延层中重复形成。形成沟槽以穿透基底层以到达外延层; 并且栅电极经由栅极绝缘膜形成在沟槽中。在基底层的周边的端部区域，在外延层上形成第二导电类型的端接层。端接层形成为具有大于基底层的结深度的结深度。

29. 发明申请

US20060157778A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20060157778A1
公开(公告)日：2006-07-20
申请号：US11305202
申请日：2005-12-19
申请人： Syotaro Ono , Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hirobumi Matsuki , Kiyotaka Arai
发明人： Syotaro Ono , Yusuke Kawaguchi , Yoshihiro Yamaguchi , Hirobumi Matsuki , Kiyotaka Arai
IPC分类号： H01L29/94
CPC分类号： H01L29/7813 , H01L29/0696
摘要： A power MOSFET includes an n-type drift layer and a p-type base layer formed in a layered manner on the n-type drift layer. Trench gates are formed to penetrate the p-type base layer to reach the n-type drift layer. On the p-type base layer, n+-type source regions and p+-type regions are formed. These n+-type source regions and p+-type regions are arranged alternately along a longitudinal direction of the trench gates. The n+-type source regions and the p+-type regions are arranged with a slant with respect to the longitudinal direction of the trench gates.
摘要翻译：功率MOSFET包括在n型漂移层上分层形成的n型漂移层和p型基极层。形成沟槽栅极以穿透p型基极层以到达n型漂移层。在p型基底层上形成n + +型源区和p + + +型区。这些n + + +型源极区域和p + + +区域沿沟槽栅极的纵向方向交替布置。相对于沟槽栅极的纵向方向，n + P +型源极区域和p + H +型区域以倾斜的方式排列。

30. 发明授权

US07067876B2 Semiconductor device 失效
公开(公告)号：US07067876B2
公开(公告)日：2006-06-27
申请号：US10139324
申请日：2002-05-07
申请人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
发明人： Norio Yasuhara , Kazutoshi Nakamura , Yusuke Kawaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/0696 , H01L29/1045 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L29/4238
摘要： A semiconductor device comprises a semiconductor substrate; a semiconductor layer having a higher resistance than that of said semiconductor substrate and provided on a top surface of said semiconductor substrate; a gate electrode provided on a gate insulating film on the top surface of said semiconductor layer; a drain layer of a first conductivity type selectively provided in a location in said semiconductor layer in one side of said gate electrode; a drain electrode connected to said drain layer; a source layer of the first conductivity type selectively provided in a location in said semiconductor layer in the other side of said gate electrode; an element-side connecting portion selectively provided on said semiconductor layer, which does not reach a channel portion between said source layer and said drain layer of said semiconductor layer and also does not reach to said semiconductor substrate, and which is in contact with said source layer and has lower resistance than that of said semiconductor layer; a contact-side connecting portion selectively provided on said semiconductor layer, having lower resistance than said semiconductor layer and extending deeper toward said semiconductor substrate than said element-side connecting portion; a first source electrode connecting said source layer, said element-side connect portion and said contact-side connect portion; and a bottom electrode provided on the bottom surface of said semiconductor substrate in connection therewith.

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