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    • 23. 发明申请
    • METHOD OF TESTING AN OBJECT AND APPARATUS FOR PERFORMING THE SAME
    • 测试对象的方法和执行该对象的设备
    • US20120150478A1
    • 2012-06-14
    • US13325154
    • 2011-12-14
    • Ki-Jae SongSung-Soo Lee
    • Ki-Jae SongSung-Soo Lee
    • G06F19/00H01L21/66G01R31/26
    • G01R31/31908G01R31/318513G01R31/31919
    • In a method of testing an object, a first test pattern for testing a first device in the object may be set in a tester. A second test pattern for testing a second device in the object may be set in a test head electrically connected between the tester and the object. The first test pattern may be provided to the first device through the test head and the second test pattern may be provided to the second device by the test head to simultaneously test the first device and the second device. Thus, the first device and the second device different from each other may be simultaneously tested without changing test conditions in the tester, so that a time for testing the object may be reduced.
    • 在测试对象的方法中,可以在测试器中设置用于测试对象中的第一设备的第一测试模式。 用于测试物体中的第二装置的第二测试图案可以设置在电连接在测试器和物体之间的测试头中。 可以通过测试头将第一测试图案提供给第一设备,并且可以由测试头将第二测试图案提供给第二设备,以同时测试第一设备和第二设备。 因此,可以在不改变测试器中的测试条件的情况下同时测试彼此不同的第一设备和第二设备,从而可以减少测试对象的时间。
    • 28. 发明申请
    • PAGE-BUFFER AND NON-VOLATILE SEMICONDUCTOR MEMORY INCLUDING PAGE BUFFER
    • PAGE-BUFFER和非易失性半导体存储器,包括页面缓冲区
    • US20100202204A1
    • 2010-08-12
    • US12752213
    • 2010-04-01
    • Sung-Soo LeeYoung-Ho LimHyun-Chul ChoDong-Hyuk Chae
    • Sung-Soo LeeYoung-Ho LimHyun-Chul ChoDong-Hyuk Chae
    • G11C16/04G11C7/10
    • G11C16/0483G11C16/26
    • In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit lines. The memory device further includes an internal data output line for outputting data read from the bit lines of the memory array, and a page buffer operatively connected between a bit line of the memory cell array and the internal data output line. The page buffer includes a sense node which is selectively connected to the bit line, a latch circuit having a latch node which is selectively connected to the sense node, a latch input path which sets a logic voltage of the latch node in the programming mode and the read mode, and a latch output path which is separate from the latch input path and which sets as logic voltage of the internal date output line according to the logic voltage of the latch node.
    • 在一个方面,提供一种可在编程模式和读取模式下操作的非易失性存储器件。 存储器件包括存储单元阵列,其包括多个非易失性存储器单元,多个字线和多个位线。 存储器件还包括用于输出从存储器阵列的位线读取的数据的内部数据输出线以及可操作地连接在存储单元阵列的位线和内部数据输出线之间的页缓冲器。 页面缓冲器包括选择性地连接到位线的感测节点,具有选择性地连接到感测节点的锁存节点的锁存电路,将锁存节点的逻辑电压设置为编程模式的锁存器输入路径,以及 读取模式和与锁存器输入路径分离并根据锁存节点的逻辑电压设置为内部日期输出线的逻辑电压的锁存器输出路径。