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21. 发明授权

US09135099B2 Memory error correction 有权
标题翻译：内存纠错
公开(公告)号：US09135099B2
公开(公告)日：2015-09-15
申请号：US13434588
申请日：2012-03-29
申请人： Yun-Han Chen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Yun-Han Chen , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C29/00 , G06F11/07 , G06F11/10 , H03M13/19 , H03M13/00
CPC分类号： G06F11/073 , G06F11/0793 , G06F11/1008 , H03M13/19 , H03M13/6561
摘要： A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.
摘要翻译：一种方法包括通过第一电路将第一格式的多个比特转换成第二格式。通过第二电路使用第二格式的多个比特来对与多个比特相对应的多个存储单元进行编程。第一种格式是并行格式。第二种格式是串行格式。第一电路和第二电路在芯片中电耦合在一起。在一些实施例中，多个位包括地址信息，单元数据信息和具有错误的存储器单元的程序信息。在一些实施例中，多个比特包括单词的字数据信息和与单词的单词数据信息对应的错误代码和校正信息。

22. 发明授权

US08760955B2 Electrical fuse memory arrays 有权
标题翻译：电熔丝存储器阵列
公开(公告)号：US08760955B2
公开(公告)日：2014-06-24
申请号：US13278686
申请日：2011-10-21
申请人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Wei-Li Liao , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/16
CPC分类号： G11C17/16 , G11C17/18
摘要： A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.
摘要翻译：重新配置eFuse存储器阵列以使两个或更多个相邻的eFuse位单元被放置在旁边并共享一个程序位线的机制。通过允许两个或多个相邻的eFuse位单元共享程序位线，程序位线的长度被缩短，这导致程序位线的电阻较低。也可以增加编程位线的宽度，以进一步降低程序位线的电阻率。使用低电阻率eFuse的高级eFuse存储器阵列需要具有低电阻和高电流的程序位线。

23. 发明申请

US20130221995A1 SENSE AMPLIFIER 有权
标题翻译：感应放大器
公开(公告)号：US20130221995A1
公开(公告)日：2013-08-29
申请号：US13407548
申请日：2012-02-28
申请人： Chen-Ming Hung , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Chen-Ming Hung , Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G01R27/08 , H03F3/45
CPC分类号： G01R27/08 , G11C7/062 , G11C17/18 , G11C2207/063 , H03F3/45179 , H03F2200/555 , H03F2203/45394 , H03F2203/45674
摘要： An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.
摘要翻译：放大电路包括偏置电路，参考电路，第一电路和放大子电路。偏置电路被配置为提供偏置电流。参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。第一电路被配置为基于第一电流和第一电阻提供第二差分输入。放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。

24. 发明授权

US08466732B2 Voltage level shifter 有权
标题翻译：电压电平转换器
公开(公告)号：US08466732B2
公开(公告)日：2013-06-18
申请号：US12900650
申请日：2010-10-08
申请人： Po-Hung Chen , Kuoyuan (Peter) Hsu , David Yen , Sung-Chieh Lin
发明人： Po-Hung Chen , Kuoyuan (Peter) Hsu , David Yen , Sung-Chieh Lin
IPC分类号： H03L5/00
CPC分类号： H03K3/356165
摘要： An input of a first inverter is configured to serve as an input node. An output of the first inverter is coupled to an input of a second inverter. An output of the second inverter is configured to serve as an output node. An input of a third inverter is coupled to an input of the first inverter. A gate of a first NMOS transistor is coupled to an output of the third inverter. A drain of the first NMOS transistor is coupled to the second inverter. A source of the first NMOS transistor is configured to serve as a level input node. When the input node is configured to receive a low logic level, the output node is configured to receive a voltage level provided by a voltage level at the level input node.
摘要翻译：第一反相器的输入被配置为用作输入节点。第一反相器的输出耦合到第二反相器的输入端。第二反相器的输出被配置为用作输出节点。第三反相器的输入耦合到第一反相器的输入端。第一NMOS晶体管的栅极耦合到第三反相器的输出端。第一NMOS晶体管的漏极耦合到第二反相器。第一NMOS晶体管的源极被配置为用作电平输入节点。当输入节点被配置为接收低逻辑电平时，输出节点被配置为接收由电平输入节点处的电压电平提供的电压电平。

25. 发明授权

US08411483B2 Testing one time programming devices 有权
标题翻译：测试一次性编程设备
公开(公告)号：US08411483B2
公开(公告)日：2013-04-02
申请号：US12833131
申请日：2010-07-09
申请人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu
发明人： Sung-Chieh Lin , Kuoyuan (Peter) Hsu
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/14 , G11C29/08
摘要： A one time programming (OTP) memory array is divided into a user section and a test section. The cells in the user section and in the test section are configured to form a checkerboard pattern, that is, having repeats of one user cell and one test cell in both column and row directions. Programming the test section and various additional tests are performed to both the user and test sections and other circuitry of the memory array while the user section is not programmed. Even though the OTP user section is not programmed or tested, the provided tests in accordance with embodiments of the invention can provide a very high probability that the OTP memory including the user section is of high quality, i.e., the OTP cells in the user section can be programmed and function appropriately.
摘要翻译：一次性编程（OTP）存储器阵列分为用户部分和测试部分。用户部分和测试部分中的单元格被配置为形成棋盘图案，即在列和行方向上具有一个用户单元和一个测试单元的重复。在用户部分未编程的情况下，对测试部分进行编程，并对存储器阵列的用户和测试部分以及其他电路进行各种附加测试。即使OTP用户部分未被编程或测试，根据本发明的实施例提供的测试可以提供包括用户部分的OTP存储器具有高质量（即，用户部分中的OTP单元）的非常高的概率可以编程并正常工作。

26. 发明授权

US07551415B2 Repair circuitry with an enhanced ESD protection device 有权
标题翻译：具有增强型ESD保护装置的修复电路
公开(公告)号：US07551415B2
公开(公告)日：2009-06-23
申请号：US11512830
申请日：2006-08-30
申请人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
发明人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
IPC分类号： H02H3/22
CPC分类号： G11C29/02 , G11C17/18 , G11C29/027
摘要： A repair circuitry consisting of at least one electrical fuse forming part of a conduction path between a positive voltage supply (Vq) pad and a complimentary lower voltage supply source (Vss). The repair circuitry includes at least one switching device and at least one control circuitry. The at least one switching device has a control terminal and is coupled between the Vq pad and the at least one electrical fuse. The at least one control circuitry is coupled to the control terminal and the Vq pad respectively. Upon an application of a positive high voltage to the Vq pad, the control circuitry delays the turned-on state of the switching device for a predetermined period of time, thereby blocking stray currents occurred during ESD events. Consequently, the repair circuitry can prevent the at least one electrical fuse from being mistakenly programmed.
摘要翻译：修复电路由至少一个电熔丝构成，形成正电压源（Vq）焊盘和互补的低电压源（Vss）之间的传导路径的一部分。修复电路包括至少一个开关装置和至少一个控制电路。所述至少一个开关装置具有控制端子，并且耦合在所述Vq焊盘和所述至少一个电熔丝之间。至少一个控制电路分别耦合到控制端子和Vq焊盘。当向Vq焊盘施加正高电压时，控制电路将开关器件的接通状态延迟预定的时间段，从而阻止在ESD事件期间发生的杂散电流。因此，修理电路可以防止至少一个电熔丝被错误编程。

27. 发明授权

US07733096B2 Methods of testing fuse elements for memory devices 失效
标题翻译：测试存储器件熔丝元件的方法
公开(公告)号：US07733096B2
公开(公告)日：2010-06-08
申请号：US11731960
申请日：2007-04-02
申请人： Sung-Chieh Lin , Po-Hung Chen
发明人： Sung-Chieh Lin , Po-Hung Chen
IPC分类号： G01R31/02
CPC分类号： G11C29/02 , G11C17/165 , G11C29/027
摘要： A method of testing a fuse element for a memory device is provided. A first test probe is electrically connected to a program terminal of the memory device. A second test probe is electrically connected to a ground terminal. The fuse element is on an electrical circuit path between the program terminal and the ground terminal. The first and second test probes are electrically connected to a testing device. A first voltage is applied with the testing device between the program terminal and the ground terminal. At least part of a first current of the first voltage flows across the fuse element. The first voltage and the at least part of the first current that flows across the fuse element is not large enough to change the conductivity state of the fuse element. The first current is measured and used to evaluated the conductive state of the fuse element.
摘要翻译：提供一种测试用于存储器件的熔丝元件的方法。第一测试探针电连接到存储器件的程序终端。第二测试探针电连接到接地端子。保险丝元件位于程序端子和接地端子之间的电路上。第一和第二测试探针电连接到测试装置。测试设备在程序终端和接地端子之间施加第一个电压。第一电压的第一电流的至少一部分流过熔丝元件。在熔断元件上流动的第一电流和第一电流的至少一部分不足以改变熔丝元件的导电状态。测量第一电流并用于评估熔丝元件的导电状态。

28. 发明申请

US20080169514A1 Stack resistor structure for integrated circuits 有权
标题翻译：集成电路的堆叠电阻结构
公开(公告)号：US20080169514A1
公开(公告)日：2008-07-17
申请号：US11652895
申请日：2007-01-11
申请人： Fu-Lung Hsueh , Sung-Chieh Lin
发明人： Fu-Lung Hsueh , Sung-Chieh Lin
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set of plugs are coupled together as a first resistor segment to provide a predetermined resistance for the integrated circuit.
摘要翻译：用于集成电路的电阻器结构包括连接在半导体层和第一导电层之间的第一组触点; 以及连接在所述第一导电层和第二导电层之间的第二组插头，其中所述第一组触点和所述第二组插头作为第一电阻器段耦合在一起以为所述集成电路提供预定电阻。

29. 发明申请

US20080062605A1 Repair circuitry with an enhanced ESD protection device 有权
标题翻译：具有增强型ESD保护装置的修复电路
公开(公告)号：US20080062605A1
公开(公告)日：2008-03-13
申请号：US11512830
申请日：2006-08-30
申请人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
发明人： Ming-Hsien Tsai , Hung-Jen Liao , Sung-Chieh Lin
IPC分类号： H02H5/04
CPC分类号： G11C29/02 , G11C17/18 , G11C29/027
摘要： A repair circuitry consisting of at least one electrical fuse forming part of a conduction path between a positive voltage supply (Vq) pad and a complimentary lower voltage supply source (Vss). The repair circuitry includes at least one switching device and at least one control circuitry. The at least one switching device has a control terminal and is coupled between the Vq pad and the at least one electrical fuse. The at least one control circuitry is coupled to the control terminal and the Vq pad respectively. Upon an application of a positive high voltage to the Vq pad, the control circuitry delays the turned-on state of the switching device for a predetermined period of time, thereby blocking stray currents occurred during ESD events. Consequently, the repair circuitry can prevent the at least one electrical fuse from being mistakenly programmed.
摘要翻译：修复电路由至少一个电熔丝构成，形成正电压源（Vq）焊盘和互补的低电压源（Vss）之间的传导路径的一部分。修复电路包括至少一个开关装置和至少一个控制电路。所述至少一个开关装置具有控制端子，并且耦合在所述Vq焊盘和所述至少一个电熔丝之间。至少一个控制电路分别耦合到控制端子和Vq焊盘。当向Vq焊盘施加正高电压时，控制电路将开关器件的接通状态延迟预定的时间段，从而阻止在ESD事件期间发生的杂散电流。因此，修理电路可以防止至少一个电熔丝被错误编程。

30. 发明授权

US07919832B2 Stack resistor structure for integrated circuits 有权
标题翻译：集成电路的堆叠电阻结构
公开(公告)号：US07919832B2
公开(公告)日：2011-04-05
申请号：US11652895
申请日：2007-01-11
申请人： Fu-Lung Hsueh , Sung-Chieh Lin
发明人： Fu-Lung Hsueh , Sung-Chieh Lin
IPC分类号： H01L29/06
CPC分类号： H01L23/5228 , H01L2924/0002 , H01L2924/00
摘要： A resistor structure for an integrated circuit includes a first set of contacts connected between a semiconductor layer and a first conductive layer; and a second set of plugs connected between the first conductive layer and a second conductive layer, wherein the first set of contacts and the second set of plugs are coupled together as a first resistor segment to provide a predetermined resistance for the integrated circuit.
摘要翻译：用于集成电路的电阻器结构包括连接在半导体层和第一导电层之间的第一组触点; 以及连接在所述第一导电层和第二导电层之间的第二组插头，其中所述第一组触点和所述第二组插头作为第一电阻器段耦合在一起以为所述集成电路提供预定电阻。

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