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21. 发明授权

US07439604B2 Method of forming dual gate dielectric layer 有权
标题翻译：形成双栅介电层的方法
公开(公告)号：US07439604B2
公开(公告)日：2008-10-21
申请号：US11616836
申请日：2006-12-27
申请人： Min-Hee Cho , Ji-Young Kim
发明人： Min-Hee Cho , Ji-Young Kim
IPC分类号： H01L29/00
CPC分类号： H01L21/823481 , H01L21/76229 , H01L21/823462
摘要： A semiconductor device includes a dual gate dielectric layer that increases a performance of a semiconductor device. The semiconductor device includes a first dielectric layer having a predetermined thickness on a semiconductor substrate. The first dielectric layer is formed on a first region. The semiconductor device also includes a second dielectric layer having a dielectric constant higher than that of the first dielectric layer. The second dielectric layer is formed on both the first region and a second region.
摘要翻译：半导体器件包括提高半导体器件的性能的双栅介质层。半导体器件包括在半导体衬底上具有预定厚度的第一电介质层。第一介电层形成在第一区域上。半导体器件还包括具有高于第一介电层的介电常数的介电常数的第二电介质层。第二介电层形成在第一区域和第二区域两者上。

22. 发明申请

US20080196515A1 CONTAMINATION ANALYSIS UNIT AND METHOD THEREOF, AND RETICLE CLEANING SYSTEM 失效
标题翻译：污染物分析单元及其方法及其清洗系统
公开(公告)号：US20080196515A1
公开(公告)日：2008-08-21
申请号：US12031086
申请日：2008-02-14
申请人： Ok-Sun Lee , Hyung-Seok Choi , Yo-Han Ahn , Ji-Young Kim
发明人： Ok-Sun Lee , Hyung-Seok Choi , Yo-Han Ahn , Ji-Young Kim
IPC分类号： G01N1/14
CPC分类号： G03F1/82 , G01N2015/0687
摘要： A contamination analysis unit and method for inspecting pollutants remaining on a target side of an inspection object such as a reticle after cleaning the object is provided. After steeping the target side in a solution, a sampling liquid may be abstracted therefrom after a predetermined time and may be analyzed.
摘要翻译：提供了一种污染分析单元和用于检查在清洁物体之后残留在诸如掩模版之类的检查对象的目标侧上的污染物的方法。在将目标侧浸入溶液中之后，可以在预定时间之后从其中抽取取样液体并进行分析。

23. 发明申请

US20080081432A1 SEMICONDUCTOR DEVICE WITH TRENCH GATE TYPE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：具有TRENCH门型晶体管的半导体器件及其制造方法
公开(公告)号：US20080081432A1
公开(公告)日：2008-04-03
申请号：US11624905
申请日：2007-01-19
申请人： Yong-Jin KIM , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
发明人： Yong-Jin KIM , Kyeong-Koo Chi , Chang-Jin Kang , Hyoung-Sub Kim , Mybong-Cheol Kim , Tae-Rin Chung , Sung-Hoon Chung , Ji-Young Kim
IPC分类号： H01L21/76
CPC分类号： H01L29/66621 , H01L21/823437 , H01L27/10876 , H01L29/7834
摘要： A semiconductor device includes a plurality of gate trenches, each of which has first inner walls, which face each other in a first direction which is perpendicular to a second direction in which active regions extend, and second inner walls, which face each other in the second direction in which the active regions extends. An isolation layer contacts a gate insulating layer throughout the entire length of the first inner wails of the gate trenches including from entrance portions of the gate trenches to bottom portions of the gate trenches, and a plurality of channel regions are disposed adjacent to the gate insulating layers in the semiconductor substrate along the second inner walls and the bottom portions of the gate trenches.
摘要翻译：半导体器件包括多个栅极沟槽，每个栅极沟槽具有第一内壁，该第一内壁沿与第一方向相对的第一方向，该第一方向垂直于有源区域延伸的第二方向;以及第二内壁，活动区域延伸的第二方向。隔离层在包括从栅极沟槽的入口部分到栅极沟槽的底部的栅极沟槽的整个长度的整个长度上接触栅极绝缘层，并且多个沟道区域邻近栅极绝缘体沿着第二内壁和栅极沟槽的底部的半导体衬底中的层。

24. 发明申请

US20070144579A1 Photovoltaic device 失效
标题翻译：光伏装置
公开(公告)号：US20070144579A1
公开(公告)日：2007-06-28
申请号：US11497353
申请日：2006-08-02
申请人： Byung-Jun Jung , Moon-Jae Lee , Dae-Won Kim , Chang-Hee Lee , Ji-Young Kim
发明人： Byung-Jun Jung , Moon-Jae Lee , Dae-Won Kim , Chang-Hee Lee , Ji-Young Kim
IPC分类号： H01L31/00
CPC分类号： H01L51/4253 , B82Y10/00 , H01L51/0037 , H01L51/0038 , H01L51/0044 , H01L51/0047 , H01L51/0053 , H01L51/0071 , H01L51/0073 , H01L51/4246 , Y02E10/549
摘要： Provided is a photovoltaic device with an organic buffer layer for efficiency improvement. The photovoltaic device includes a first electrode and a second electrode disposed opposite to each other, a photoactive layer disposed between the first electrode and the second electrode, and a buffer layer disposed between the photoactive layer and the second electrode. The buffer layer includes a compound including an aromatic organic cation and an anion in a quantity ranging from 30 wt % to 100 wt %, more preferably 50 wt % to 100 wt % with respect to the entire weight of the buffer layer.
摘要翻译：提供了一种具有有机缓冲层以提高效率的光伏器件。光电器件包括彼此相对设置的第一电极和第二电极，设置在第一电极和第二电极之间的光敏层，以及设置在光敏层和第二电极之间的缓冲层。相对于缓冲层的整个重量，缓冲层包括含有30重量％〜100重量％，更优选50重量％〜100重量％的芳香族有机阳离子和阴离子的化合物。

25. 发明申请

US20060202340A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20060202340A1
公开(公告)日：2006-09-14
申请号：US11279080
申请日：2006-04-07
申请人： Byung-Jun Park , Ji-Young Kim
发明人： Byung-Jun Park , Ji-Young Kim
IPC分类号： H01L23/52
CPC分类号： H01L21/76877 , H01L21/76831 , H01L21/76895 , H01L21/76897 , H01L27/0207 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： Wirings including first conductive layer patterns and insulating mask layer patterns are formed on a substrate. Insulating spacers are formed on sidewalls of the wirings. Self-aligned contact pads including portions of a second conductive layer are formed to contact with surfaces of the insulating spacers and to fill up a gap between the wirings. An interlayer dielectric layer is formed on the substrate where the contact pads are formed and is then partially etched to form contact holes exposing the contact pads. A selective epitaxial silicon layer is formed on the contact pads exposed through the contact holes to cover the insulating mask layer patterns. Thus, a short-circuit between the lower wiring and an upper wiring formed in the contact holes is prevented.
摘要翻译：在基板上形成包括第一导电层图案和绝缘掩模层图案的布线。绝缘垫片形成在布线的侧壁上。形成包括第二导电层的部分的自对准接触焊盘与绝缘间隔物的表面接触并填充布线之间的间隙。在形成接触焊盘的基板上形成层间电介质层，然后将其部分地蚀刻以形成暴露接触焊盘的接触孔。在通过接触孔暴露的接触焊盘上形成选择性外延硅层以覆盖绝缘掩模层图案。因此，防止下布线和形成在接触孔中的上布线之间的短路。

26. 发明授权

US07060574B2 Buried channel type transistor having a trench gate and method of manufacturing the same 有权
公开(公告)号：US07060574B2
公开(公告)日：2006-06-13
申请号：US10839951
申请日：2004-05-05
申请人： Ji-Young Kim , Chang-Sub Lee
发明人： Ji-Young Kim , Chang-Sub Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/105 , H01L29/1083 , H01L29/6659 , H01L29/66621 , H01L29/7834
摘要： In a method of manufacturing a buried channel type transistor, a trench is formed at a surface portion of a substrate. A first and a second threshold voltage control regions are formed at portions of the substrate beneath a bottom face of the trench and adjacent to a sidewall of the trench, respectively. A gate electrode filling the trench is formed. Source/drain regions are formed at portions of the substrate adjacent to the sidewall of the gate electrode. Stopper regions are formed at portions of the substrate beneath the source/drain regions and beneath the first and second threshold voltage control regions, respectively. The buried channel type transistor has a high breakdown voltage between the source/drain regions although a threshold voltage thereof is low.

27. 发明授权

US06960507B2 Vertical double-channel silicon-on-insulator transistor and method of manufacturing the same 有权
标题翻译：垂直双通道绝缘体上硅晶体管及其制造方法
公开(公告)号：US06960507B2
公开(公告)日：2005-11-01
申请号：US10759239
申请日：2004-01-20
申请人： Ji-Young Kim , Jin-Jun Park
发明人： Ji-Young Kim , Jin-Jun Park
IPC分类号： H01L21/762 , H01L21/336 , H01L21/76 , H01L21/8234 , H01L27/088 , H01L27/11 , H01L29/423 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66787 , H01L29/42384 , H01L29/78696
摘要： A vertical double channel silicon-on-insulator (SOI) field-effect-transistor (FET) includes a pair of two vertical semiconductor layers in contact with a pair of parallel shallow trench isolation layers on a substrate, a source, a drain and a channel region on each of the pair of vertical semiconductor layers with corresponding regions on the pair of vertical semiconductor layers facing each other in alignment, a gate oxide on the channel region of both of the pair of the vertical semiconductor layers, and a gate electrode, a source electrode, and a drain electrode electrically connecting the respective regions of the pair of vertical semiconductor layers.
摘要翻译：垂直双通道绝缘体上硅（SOI）场效应晶体管（FET）包括与衬底上的一对平行浅沟槽隔离层接触的一对两个垂直半导体层，源极，漏极和漏极所述一对垂直半导体层中的每一个上的沟道区域与所述一对垂直半导体层中的对置区域对准，所述一对垂直半导体层中的两个沟道区上的栅极氧化物和栅电极，源极电极和漏电极，电连接所述一对垂直半导体层的各个区域。

28. 发明申请

US20050213384A1 Semiconductor device and method of forming the same 审中-公开
标题翻译：半导体器件及其形成方法
公开(公告)号：US20050213384A1
公开(公告)日：2005-09-29
申请号：US11135775
申请日：2005-05-23
申请人： Ji-Young Kim , Sang-Yong Kim
发明人： Ji-Young Kim , Sang-Yong Kim
IPC分类号： H01L29/78 , H01L21/8234 , H01L23/31 , G11C11/34
CPC分类号： H01L29/6656 , H01L21/823437 , H01L21/823468 , H01L23/3171 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device protecting the ends of a gate line and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate, a gate line crossing over the semiconductor substrate, and a protecting pattern covering ends of the gate line. According to the method, a gate line is formed at a semiconductor substrate. A spacer is formed to cover sidewalls of the gate line. A protecting pattern is formed to cover the ends of the gate line. The protecting pattern may be formed of silicon nitride or silicon oxide. Since the protecting pattern protects ends of a gate line, it is possible to prevent gate electrodes from being damaged by a cleaning solution such as SC1 in a subsequent process.
摘要翻译：公开了保护栅极线的端部的半导体器件及其形成方法。半导体器件包括半导体衬底，跨越半导体衬底的栅极线和覆盖栅极线的端部的保护图案。根据该方法，在半导体衬底上形成栅极线。形成间隔件以覆盖栅极线的侧壁。形成保护图案以覆盖栅极线的端部。保护图案可以由氮化硅或氧化硅形成。由于保护图案保护栅极线的端部，因此可以防止在随后的工艺中栅电极被诸如SC1的清洁溶液损坏。

29. 发明授权

US06903404B2 Semiconductor memory device and method for manufacturing the same 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06903404B2
公开(公告)日：2005-06-07
申请号：US10426153
申请日：2003-04-29
申请人： Ji-Young Kim
发明人： Ji-Young Kim
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/331 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/73
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/10808 , H01L27/10885 , H01L27/10888
摘要： A semiconductor memory device includes a plurality of bit line structures arranged in parallel on a semiconductor substrate and having a plurality of bit lines and an insulating material surrounding the bit lines, an isolation layer formed in a portion in spaces between the bit line structures to define a predetermined active region and having substantially the same height as the bit line structures, a semiconductor layer formed in the predetermined active region surrounded by the bit line structures and the isolation layer and having substantially the same height as the bit line structures and the isolation layer, a plurality of word line structures arranged in parallel on the bit line structures, the isolation layer, and the semiconductor layer, and comprising a plurality of word lines and an insulating material surrounding the word lines, and source and drain regions formed in the semiconductor layer on either side of the word line structures.
摘要翻译：半导体存储器件包括多个位线结构并行布置在半导体衬底上并且具有多个位线和围绕位线的绝缘材料，隔离层形成在位线结构之间的空间部分中以限定预定的有源区并且具有与位线结构基本相同的高度;形成在由位线结构和隔离层围绕的预定有源区中并且具有与位线结构和隔离层基本相同的高度的半导体层，在位线结构，隔离层和半导体层上平行布置的多个字线结构，并且包括多个字线和围绕字线的绝缘材料，以及形成在半导体中的源极和漏极区域在字线结构的任一侧的层。

30. 发明申请

US20050098850A1 Semiconductor device with self-aligned junction contact hole and method of fabricating the same 有权
标题翻译：具有自对准接合孔的半导体器件及其制造方法
公开(公告)号：US20050098850A1
公开(公告)日：2005-05-12
申请号：US11009913
申请日：2004-12-10
申请人： Ji-Young Kim , Je-Min Park
发明人： Ji-Young Kim , Je-Min Park
IPC分类号： H01L21/28 , H01L21/336 , H01L21/60 , H01L21/76 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L21/8247 , H01L27/08 , H01L27/088 , H01L27/115 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L21/76897 , H01L21/76229 , H01L21/823481
摘要： A plurality of trenches for defining active regions are formed in a semiconductor substrate, using a plurality of trench masks. A gap fill insulating layer is formed on the resulting structure to fill a gap region bounded by the trench and the trench masks. Next, the trench mask and the gap fill insulating layer are patterned to form a trench mask pattern and a gap fill insulating pattern for defining a slit-type opening, extending across and exposes the active region. A gate pattern is formed in the slit-type opening and the trench mask pattern is removed to form a contact opening exposing the active region. Next, a contact plug is formed to fill the contact opening. Here, the contact opening is self-alignedly formed using an etch selectivity between the trench mask and the gap fill insulating layer. The resulting contact opening is a vacancy in a rectangular parallelepiped shape.
摘要翻译：使用多个沟槽掩模在半导体衬底中形成用于限定有源区的多个沟槽。在所得结构上形成间隙填充绝缘层，以填充由沟槽和沟槽掩模界定的间隙区域。接下来，将沟槽掩模和间隙填充绝缘层图案化以形成沟槽掩模图案和间隙填充绝缘图案，用于限定狭缝型开口，延伸跨过并暴露活性区域。在狭缝型开口中形成栅极图案，并且去除沟槽掩模图案以形成暴露有源区的接触开口。接下来，形成接触插塞以填充接触开口。这里，使用沟槽掩模和间隙填充绝缘层之间的蚀刻选择性，自对准地形成接触开口。所形成的接触开口是长方体形状的空位。

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