专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20080011999A1 Microelectronic Devices Using Sacrificial Layers and Structures Fabricated by Same 有权
标题翻译：使用牺牲层的微电子器件和由其制造的结构
公开(公告)号：US20080011999A1
公开(公告)日：2008-01-17
申请号：US11860674
申请日：2007-09-25
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

22. 发明授权

US07223693B2 Methods for fabricating memory devices using sacrificial layers and memory devices fabricated by same 失效
标题翻译：用于制造使用牺牲层的存储器件和由其制造的存储器件的方法
公开(公告)号：US07223693B2
公开(公告)日：2007-05-29
申请号：US11168894
申请日：2005-06-28
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son
IPC分类号： H01L21/00
CPC分类号： H01L21/7684 , H01L21/76816 , H01L21/76831 , H01L21/76883 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： Methods are provided for fabricating contacts in integrated circuit devices, such as phase-change memories. A protection layer and a sacrificial layer are sequentially formed on a semiconductor substrate. A contact hole is formed through the sacrificial layer and the protection layer. A conductive layer is formed on the sacrificial layer and in the contact hole, and portions of the conductive layer and the sacrificial layer are removed to expose the protection layer and form a conductive plug protruding from the protection layer. A protruding portion of the conductive plug removed to leave a contact plug in the protection layer. A phase-change data storage element may be formed on the contact plug.
摘要翻译：提供了用于在诸如相变存储器的集成电路器件中制造触点的方法。在半导体衬底上依次形成保护层和牺牲层。通过牺牲层和保护层形成接触孔。在牺牲层和接触孔中形成导电层，并且去除导电层和牺牲层的部分以露出保护层并形成从保护层突出的导电插塞。去除导电塞的突出部分，以在保护层中留下接触塞。可以在接触插塞上形成相变数据存储元件。

23. 发明申请

US20050130414A1 Methods for forming small features in microelectronic devices using sacrificial layers and structures fabricated by same 失效
标题翻译：在使用牺牲层和由其制造的结构的微电子器件中形成小特征的方法
公开(公告)号：US20050130414A1
公开(公告)日：2005-06-16
申请号：US10873388
申请日：2004-06-22
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L21/28 , H01L21/20 , H01L21/44 , H01L27/24 , H01L45/00
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

24. 发明授权

US08723297B2 Memory device 有权
标题翻译：内存设备
公开(公告)号：US08723297B2
公开(公告)日：2014-05-13
申请号：US13177984
申请日：2011-07-07
申请人： Yoon-Ho Son , Mong-Sup Lee , In-Seak Hwang , Dae-Hyuk Chung , Suk-Hun Choi , Sang-Jun Lee
发明人： Yoon-Ho Son , Mong-Sup Lee , In-Seak Hwang , Dae-Hyuk Chung , Suk-Hun Choi , Sang-Jun Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/10888 , H01L21/02057 , H01L21/02063 , H01L21/30608 , H01L21/76805 , H01L21/76814 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L29/1037 , H01L29/41766 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.
摘要翻译：在具有接触结构和衬底之间的扩大的接触面积的半导体器件中，衬底可以包括布置有导电结构的第一区域和限定第一区域的第二区域。第一区域可以包括多面多面体凹部，其中至少一个侧壁相对于基底的表面倾斜。可以在衬底上形成足够覆盖导电结构的厚度的绝缘层。绝缘层具有可与凹部连通的接触孔。基板的有源区域通过接触孔露出。导电图案位于凹槽和接触孔中。因此，即使图案线的间隙距离和线宽减小，也可以将基板的有源区域的接触电阻保持在较低的值。

25. 发明授权

US08357613B2 Methods of fabricating semiconductor devices and semiconductor devices including a contact plug processed by rapid thermal annealing 有权
标题翻译：制造半导体器件和包括通过快速热退火处理的接触插塞的半导体器件的方法
公开(公告)号：US08357613B2
公开(公告)日：2013-01-22
申请号：US12656673
申请日：2010-02-12
申请人： Suk-Hun Choi , Chang-Ki Hong , Jae-Hyoung Choi , Yoon-Ho Son , Min-Young Park , Yong-Suk Tak
发明人： Suk-Hun Choi , Chang-Ki Hong , Jae-Hyoung Choi , Yoon-Ho Son , Min-Young Park , Yong-Suk Tak
IPC分类号： H01L21/44
CPC分类号： H01L21/76877 , H01L21/321 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (WξOψ).
摘要翻译：制造半导体器件的方法包括在绝缘层上沉积钨，其中通过化学气相沉积（CVD）形成接触孔，在钨上进行化学机械平面化（CMP）以暴露绝缘层并形成钨接触插塞，并且在氧气氛中对钨接触塞进行快速热氧化（RTO），使得钨以体积方式膨胀成氧化钨（W＆Xgr;Oψ）。

26. 发明申请

US20120025283A1 MEMORY DEVICE 有权
标题翻译：内存设备
公开(公告)号：US20120025283A1
公开(公告)日：2012-02-02
申请号：US13177984
申请日：2011-07-07
申请人： Yoon-Ho Son , Mong-Sup Lee , In-Seak Hwang , Dae-Hyuk Chung , Suk-Hun Choi , Sang-Jun Lee
发明人： Yoon-Ho Son , Mong-Sup Lee , In-Seak Hwang , Dae-Hyuk Chung , Suk-Hun Choi , Sang-Jun Lee
IPC分类号： H01L27/108 , H01L29/06
CPC分类号： H01L27/10888 , H01L21/02057 , H01L21/02063 , H01L21/30608 , H01L21/76805 , H01L21/76814 , H01L21/76897 , H01L23/485 , H01L27/10814 , H01L27/10855 , H01L29/1037 , H01L29/41766 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device having an enlarged contact area between a contact structure and a substrate, the substrate may include a first region on which a conductive structure is arranged and a second region defining the first region. The first region may include a multi-faced polyhedral recess of which at least one of the sidewalls is slanted with respect to a surface of the substrate. An insulation layer may be formed on the substrate to a thickness that is sufficient to cover the conductive structure. The insulation layer has a contact hole that may be communicated with the recess. The active region of the substrate is exposed through the contact hole. A conductive pattern is positioned in the recess and the contact hole. Accordingly, the contact resistance at the active region of the substrate may be kept to a relatively low value even though the gap distances and line width of pattern lines are reduced.
摘要翻译：在具有接触结构和衬底之间的扩大的接触面积的半导体器件中，衬底可以包括布置有导电结构的第一区域和限定第一区域的第二区域。第一区域可以包括多面多面体凹部，其中至少一个侧壁相对于基底的表面倾斜。可以在衬底上形成足够覆盖导电结构的厚度的绝缘层。绝缘层具有可与凹部连通的接触孔。基板的有源区域通过接触孔露出。导电图案位于凹槽和接触孔中。因此，即使图案线的间隙距离和线宽减小，也可以将基板的有源区域的接触电阻保持在较低的值。

27. 发明授权

US07803657B2 Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same 有权
标题翻译：制造可变电阻结构的方法以及使用其制造相变存储器件的方法
公开(公告)号：US07803657B2
公开(公告)日：2010-09-28
申请号：US12654714
申请日：2009-12-30
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
IPC分类号： H01L21/44 , H01L29/08 , H01L29/18
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.
摘要翻译：在制造可变电阻结构和相变存储器件的方法中，在具有接触区域的基板上形成第一绝缘层之后，通过第一绝缘层形成暴露接触区域的接触孔。在第一绝缘层上形成第一导电层以填充接触孔之后，在第一导电层上形成第一保护层图案。部分地蚀刻第一导电层以形成接触并在接触件上形成焊盘。在第一保护层图案上形成第二保护层，然后通过第二保护层和第一保护层图案形成露出焊盘的开口。在形成第一电极之后，在第一电极和第二保护层上形成相变材料层图案和第二电极。

28. 发明申请

US20100203725A1 Methods of fabricating semiconductor devices and semiconductor devices including a contact plug processed by rapid thermal annealing 有权
标题翻译：制造半导体器件和包括通过快速热退火处理的接触插塞的半导体器件的方法
公开(公告)号：US20100203725A1
公开(公告)日：2010-08-12
申请号：US12656673
申请日：2010-02-12
申请人： Suk-Hun Choi , Chang-Ki Hong , Jae-Hyoung Choi , Yoon-Ho Son , Min-Young Park , Yong-Suk Tak
发明人： Suk-Hun Choi , Chang-Ki Hong , Jae-Hyoung Choi , Yoon-Ho Son , Min-Young Park , Yong-Suk Tak
IPC分类号： H01L21/768
CPC分类号： H01L21/76877 , H01L21/321 , H01L21/3212 , H01L21/7684 , H01L21/76883
摘要： A method of fabricating a semiconductor device includes depositing tungsten on an insulating layer in which a contact hole is formed by chemical vapor deposition (CVD), performing chemical mechanical planarization (CMP) on the tungsten to expose the insulating layer and form a tungsten contact plug, and performing rapid thermal oxidation (RTO) on the tungsten contact plug in an oxygen atmosphere such that the tungsten expands volumetrically into tungsten oxide (WξOψ).
摘要翻译：制造半导体器件的方法包括在绝缘层上沉积钨，其中通过化学气相沉积（CVD）形成接触孔，在钨上进行化学机械平面化（CMP）以暴露绝缘层并形成钨接触插塞，并且在氧气氛中对钨接触塞进行快速热氧化（RTO），使得钨以体积方式膨胀成氧化钨（W＆Xgr;Oψ）。

29. 发明申请

US20100112752A1 Method of manufacturing a variable resistance structure and method of manufacturing a phase-change memory device using the same 有权
公开(公告)号：US20100112752A1
公开(公告)日：2010-05-06
申请号：US12654714
申请日：2009-12-30
申请人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
发明人： Suk-Hun Choi , Chang-Ki Hong , Yoon-Ho Son , Jang-Eun Heo
IPC分类号： H01L21/06
CPC分类号： H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： In methods of manufacturing a variable resistance structure and a phase-change memory device, after forming a first insulation layer on a substrate having a contact region, a contact hole exposing the contact region is formed through the first insulation layer. After forming a first conductive layer on the first insulation layer to fill up the contact hole, a first protection layer pattern is formed on the first conductive layer. The first conductive layer is partially etched to form a contact and to form a pad on the contact. A second protection layer is formed on the first protection layer pattern, and then an opening exposing the pad is formed through the second protection layer and the first protection layer pattern. After formation of a first electrode, a phase-change material layer pattern and a second electrode are formed on the first electrode and the second protection layer.

30. 发明授权

US07612359B2 Microelectronic devices using sacrificial layers and structures fabricated by same 有权
标题翻译：使用牺牲层的微电子器件和由其制造的结构
公开(公告)号：US07612359B2
公开(公告)日：2009-11-03
申请号：US11860674
申请日：2007-09-25
申请人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
发明人： Suk-Hun Choi , Yoon-Ho Son , Sung-Lae Cho , Joon-Sang Park
IPC分类号： H01L29/02
CPC分类号： H01L45/06 , H01L27/2436 , H01L45/1233 , H01L45/126 , H01L45/16
摘要： A dielectric layer is formed on a region of a microelectronic substrate. A sacrificial layer is formed on the dielectric layer, and portions of the sacrificial layer and the dielectric layer are removed to form an opening that exposes a portion of the region. A conductive layer is formed on the sacrificial layer and in the opening. Portions of the sacrificial layer and the conductive layer on the dielectric layer are removed to leave a conductive plug in the dielectric layer and in contact with the region. Removal of the sacrificial layer and portions of the conductive layer on the dielectric layer may include polishing to expose the sacrificial layer and to leave a conductive plug in the sacrificial layer and the dielectric layer, etching the sacrificial layer to expose the dielectric layer and leave a portion of the conductive plug protruding from the dielectric layer, and polishing to remove the protruding portion of the conductive plug. Phase-change memory devices formed by such techniques are also discussed.
摘要翻译：在微电子基板的区域上形成介电层。在电介质层上形成牺牲层，去除牺牲层和电介质层的部分以形成露出该区域的一部分的开口。在牺牲层和开口中形成导电层。去除部分牺牲层和电介质层上的导电层，以在电介质层中留下导电插塞并与该区域接触。消除牺牲层和电介质层上的导电层的部分可以包括抛光以暴露牺牲层并在牺牲层和电介质层中留下导电插塞，蚀刻牺牲层以暴露电介质层并留下导电插头从电介质层突出的部分，并且抛光以去除导电插塞的突出部分。还讨论了通过这种技术形成的相变存储器件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式