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21. 发明授权

US07999746B2 Printed circuit board having built-in antenna 有权
标题翻译：具有内置天线的印刷电路板
公开(公告)号：US07999746B2
公开(公告)日：2011-08-16
申请号：US12285315
申请日：2008-10-01
申请人： Won-Woo Cho , Jae-Suk Sung , Jae-Youb Jung , Dek-Gin Yang , Ju-Hyung Kim
发明人： Won-Woo Cho , Jae-Suk Sung , Jae-Youb Jung , Dek-Gin Yang , Ju-Hyung Kim
IPC分类号： H01Q1/38
CPC分类号： H01Q1/243 , H01Q1/38 , H01Q5/371 , H01Q9/42 , H05K1/16 , H05K2201/10098
摘要： A printed circuit board having a built-in antenna may include a first unit substrate, in which a ground and a first radiator are formed; a second unit substrate, which is stacked over the first unit substrate, and in which a second radiator having a frequency band different from a frequency band of the first radiator is formed; a pair of striplines, formed in the first unit substrate and connected with the ground; a first via, which connects the first radiator with the second radiator; a pair of second vias, each of which has one end connected with the pair of strip lines respectively; and a connection pattern, which connects the other ends of the pair of second vias to each other. The printed circuit board having a built-in antenna can utilize multiple frequency bands, and can be implemented in a compact size, to be applicable in compact communication devices.
摘要翻译：具有内置天线的印刷电路板可以包括其中形成有接地和第一散热器的第一单元基板; 第二单元基板，层叠在所述第一单元基板上，并且形成具有与所述第一散热器的频带不同的频带的第二辐射体; 一对带状线，形成在第一单元基板上并与地相连; 连接第一散热器和第二散热器的第一通孔; 一对第二通孔，每个第二通孔的一端分别与一对带状线连接; 以及将一对第二通孔的另一端彼此连接的连接图案。具有内置天线的印刷电路板可以利用多个频带，并且可以以紧凑的尺寸实现，以适用于紧凑的通信设备。

22. 发明申请

US20090140931A1 Printed Circuit board having built-in antenna 有权
标题翻译：具有内置天线的印刷电路板
公开(公告)号：US20090140931A1
公开(公告)日：2009-06-04
申请号：US12285315
申请日：2008-10-01
申请人： Won-Woo Cho , Jae-Suk Sung , Jae-Youb Jung , Dek-Gin Yang , Ju-Hyung Kim
发明人： Won-Woo Cho , Jae-Suk Sung , Jae-Youb Jung , Dek-Gin Yang , Ju-Hyung Kim
IPC分类号： H01Q1/38
CPC分类号： H01Q1/243 , H01Q1/38 , H01Q5/371 , H01Q9/42 , H05K1/16 , H05K2201/10098
摘要： A printed circuit board having a built-in antenna may include a first unit substrate, in which a ground and a first radiator are formed; a second unit substrate, which is stacked over the first unit substrate, and in which a second radiator having a frequency band different from a frequency band of the first radiator is formed; a pair of striplines, formed in the first unit substrate and connected with the ground; a first via, which connects the first radiator with the second radiator; a pair of second vias, each of which has one end connected with the pair of strip lines respectively; and a connection pattern, which connects the other ends of the pair of second vias to each other. The printed circuit board having a built-in antenna can utilize multiple frequency bands, and can be implemented in a compact size, to be applicable in compact communication devices.
摘要翻译：具有内置天线的印刷电路板可以包括其中形成有接地和第一散热器的第一单元基板; 第二单元基板，层叠在所述第一单元基板上，并且形成具有与所述第一散热器的频带不同的频带的第二辐射体; 一对带状线，形成在第一单元基板上并与地相连; 连接第一散热器和第二散热器的第一通孔; 一对第二通孔，每个第二通孔的一端分别与一对带状线连接; 以及将一对第二通孔的另一端彼此连接的连接图案。具有内置天线的印刷电路板可以利用多个频带，并且可以以紧凑的尺寸实现，以适用于紧凑的通信设备。

23. 发明申请

US20070272971A1 Non-Volatile Memory Device and Method of Fabricating the Same 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070272971A1
公开(公告)日：2007-11-29
申请号：US11734659
申请日：2007-04-12
申请人： Chang-Hyun Lee , Tea-Kwang Yu , Jong-Sun Sel , Ju-Hyung Kim , Byeong-In Choe
发明人： Chang-Hyun Lee , Tea-Kwang Yu , Jong-Sun Sel , Ju-Hyung Kim , Byeong-In Choe
IPC分类号： H01L29/788
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11526 , H01L27/11541
摘要： In the non-volatile memory device, a first isolation layer is formed to have a plurality of depressions each having a predetermined depth from an upper surface of the semiconductor substrate. A fin type first active region is defined by the first isolation layer and has one or more inflected portions at its sidewalls exposed from the first isolation layer, where the first active region is divided into an upper part and a lower part by the inflected portions and a width of the upper part is narrower than that of the lower part. A tunneling insulation layer is formed on the first active region. A storage node layer is formed on the tunneling insulation layer. Also, a blocking insulation layer is formed on the storage node layer, and a control gate electrode is formed on the blocking insulation layer.
摘要翻译：在非易失性存储器件中，第一隔离层形成为具有从半导体衬底的上表面具有预定深度的多个凹部。翅片型第一有源区由第一隔离层限定，并且在其侧壁处具有从第一隔离层露出的一个或多个弯曲部分，其中第一有源区被折弯部分分成上部和下部，上部的宽度比下部的宽度窄。隧道绝缘层形成在第一有源区上。在隧道绝缘层上形成存储节点层。此外，在存储节点层上形成隔离绝缘层，并且在阻挡绝缘层上形成控制栅电极。

24. 发明申请

US20070063739A1 Pre-emphasis apparatus, low voltage differential signaling transmitter including the same and pre-emphasis method 有权
标题翻译：预加重装置，低压差分信号发射机包括相同的预加重方法
公开(公告)号：US20070063739A1
公开(公告)日：2007-03-22
申请号：US11503311
申请日：2006-08-11
申请人： Ju-Hyung Kim
发明人： Ju-Hyung Kim
IPC分类号： H03K19/094
CPC分类号： H04L25/0272 , H03K19/0185
摘要： A pre-emphasis apparatus of a LVDS transmitter includes a pre-emphasis signaling generation unit and a pre-emphasis current output unit. The pre-emphasis signal generation unit generates a pre-emphasis pulse signal based on N parallel data signals received from an external source and N-phase clock signals received from a phase locked loop, where N is an integer greater than 1. The pre-emphasis current output unit provides an additional current for a pre-emphasis operation to a current source of a LVDS driver in response to the pre-emphasis pulse signal generated by the pre-emphasis pulse signal generation unit. The pulse signal for pre-emphasis is generated based on the parallel data signals received from the external source and the multi-phase clock signals, which are output from the phase locked loop for performing a sampling of the parallel data signals.
摘要翻译： LVDS发射机的预加重装置包括预加重信令产生单元和预加重电流输出单元。预加重信号产生单元基于从外部源接收的N个并行数据信号和从锁相环接收的N相时钟信号产生预加重脉冲信号，其中N是大于1的整数。强调电流输出单元响应于由预加重脉冲信号产生单元产生的预加重脉冲信号，向LVDS驱动器的电流源提供用于预加重操作的附加电流。用于预加重的脉冲信号基于从外部源接收的并行数据信号和从锁相环输出的并行数据信号的采样的多相时钟信号产生。

25. 发明授权

US06606067B2 Apparatus for wideband directional antenna 有权
公开(公告)号：US06606067B2
公开(公告)日：2003-08-12
申请号：US09985097
申请日：2001-11-01
申请人： Jeong-Kun Oh , Yong-Hee Lee , Byung-Il Oh , Woon-Phil Kim , Ju-Hyung Kim
发明人： Jeong-Kun Oh , Yong-Hee Lee , Byung-Il Oh , Woon-Phil Kim , Ju-Hyung Kim
IPC分类号： H01Q1310
CPC分类号： H01Q1/38 , H01Q7/00 , H01Q9/16 , H01Q9/265
摘要： Disclosed is a wideband directional antenna in a wireless communication service, comprising at least one radiation element, wherein the radiation element includes at least one loop, wherein one feeding point of the loop is connected to feeder and the other feeding point is connected to a ground distributor.

26. 发明申请

US20150060979A1 VERTICAL MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：垂直存储器件及其制造方法
公开(公告)号：US20150060979A1
公开(公告)日：2015-03-05
申请号：US14471619
申请日：2014-08-28
申请人： Gil-Sung Lee , Chang-Seok Kang , Ju-Hyung Kim
发明人： Gil-Sung Lee , Chang-Seok Kang , Ju-Hyung Kim
IPC分类号： H01L27/115 , H01L29/10 , H01L29/423
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/105 , H01L29/42356
摘要： A vertical memory device includes a channel and gate electrodes. The channel extends in a vertical direction with respect to a top surface of a substrate. The gate electrodes are disposed on an outer sidewall of the channel. The gate electrodes includes a ground selection line (GSL), a word line, a string selection line (SSL) and a first dummy word line sequentially stacked from the top surface of the substrate in the vertical direction to be spaced apart from each other. The channel includes an impurity region at a portion adjacent to the SSL.
摘要翻译：垂直存储器件包括沟道和栅电极。通道相对于基板的顶表面在垂直方向上延伸。栅电极设置在通道的外侧壁上。栅极电极包括从基板的上表面沿垂直方向依次堆叠的接地选择线（GSL），字线，串选择线（SSL）和第一虚拟字线，以彼此间隔开。该通道在与SSL相邻的部分包括杂质区域。

27. 发明授权

US08581761B1 Methods and apparatus for performing code correction for hybrid analog-to-digital converters in imaging devices 有权
标题翻译：用于对成像装置中的混合模数转换器执行代码校正的方法和装置
公开(公告)号：US08581761B1
公开(公告)日：2013-11-12
申请号：US13650434
申请日：2012-10-12
申请人： Ashirwad Bahukhandi , Taehee Cho , Ju-Hyung Kim
发明人： Ashirwad Bahukhandi , Taehee Cho , Ju-Hyung Kim
IPC分类号： H03M1/06
CPC分类号： H03M1/0863 , H03M1/145 , H03M1/466 , H03M1/56
摘要： Electronic devices may include image sensors having image sensor pixels. The pixels may be coupled to analog to digital converter (ADC) circuitry. The ADC may include a hybrid successive approximation register (SAR) ADC and ramp-compare ADC. The ramp-compare ADC may be controlled by count bits. The hybrid ADC may be subject to non-idealities at the transition between data conversion using the SAR ADC and the ramp-compare ADC. A voltage offset may be injected to the ramp-compare ADC to compensate for voltage glitches. The ramp-compare ADC may have an output range that is insufficiently matched to a least significant bit of the SAR ADC. An error correction bit may be added to the count bits to increase the output range of the ramp-compare ADC to match the SAR least significant bit. The ramp-compare ADC may include gain control circuitry to further match the output range to the SAR least significant bit.
摘要翻译：电子设备可以包括具有图像传感器像素的图像传感器。像素可以耦合到模数转换器（ADC）电路。 ADC可以包括混合逐次逼近寄存器（SAR）ADC和斜坡比较ADC。斜坡比较ADC可以通过计数位来控制。在使用SAR ADC和斜坡比较ADC的数据转换之间的转换时，混合ADC可能会受到非理想性的影响。电压偏移可以注入斜坡比较ADC以补偿电压毛刺。斜坡比较ADC可能具有与SAR ADC的最低有效位不足匹配的输出范围。可以向计数位添加纠错位，以增加斜坡比较ADC的输出范围以匹配SAR最低有效位。斜坡比较ADC可以包括增益控制电路，以进一步将输出范围与SAR最低有效位匹配。

28. 发明申请

US20130228849A1 NONVOLATILE MEMORY DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20130228849A1
公开(公告)日：2013-09-05
申请号：US13775833
申请日：2013-02-25
申请人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
发明人： Ju-Hyung Kim , Chang-Seok Kang , Woon-Kyung Lee
IPC分类号： H01L29/792 , H01L29/66
CPC分类号： H01L29/792 , H01L27/11582 , H01L29/4234 , H01L29/513 , H01L29/66833 , H01L29/7926
摘要： A nonvolatile memory device comprises a channel pattern, a first interlayer dielectric film and a second interlayer dielectric film spaced apart from each other and stacked over each other, a gate pattern disposed between the first interlayer dielectric film and the second interlayer dielectric film, a trap layer disposed between the gate pattern and the channel pattern and a charge spreading inhibition layer disposed between the channel pattern and the first interlayer dielectric film and between the channel pattern and the second interlayer dielectric film. The charge spreading inhibition layer may include charges inside or on its surface. The charge spreading inhibition layer includes at least one of a metal oxide film or a metal nitride film or a metal oxynitride film having a greater dielectric constant than a silicon oxide film.
摘要翻译：非易失性存储器件包括彼此间隔开并且彼此堆叠的沟道图案，第一层间电介质膜和第二层间电介质膜，布置在第一层间电介质膜和第二层间电介质膜之间的栅极图案，阱设置在栅极图案和沟道图案之间的层，以及设置在沟道图案和第一层间电介质膜之间以及沟道图案和第二层间电介质膜之间的电荷扩展抑制层。电荷扩散抑制层可以包括其表面内部或其表面上的电荷。电荷扩散抑制层包括金属氧化物膜或金属氮化物膜或具有比氧化硅膜更大的介电常数的金属氧氮化物膜中的至少一种。

29. 发明申请

US20120068245A1 NON-VOLATILE MEMORY DEVICES INCLUDING BLOCKING INSULATION PATTERNS WITH SUB-LAYERS HAVING DIFFERENT ENERGY BAND GAPS 有权
标题翻译：非易失性存储器件，包括具有不同能量带GAAS的子层的阻塞绝缘图案
公开(公告)号：US20120068245A1
公开(公告)日：2012-03-22
申请号：US13305930
申请日：2011-11-29
申请人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
发明人： Ju-Hyung Kim , Sung-Il Chang , Chang-Seok Kang , Jung-Dal Choi
IPC分类号： H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11517 , H01L27/11529 , H01L27/11563 , H01L27/11568 , H01L29/42324 , H01L29/4234 , H01L29/42348 , H01L29/51 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/788 , H01L29/7883
摘要： A non-volatile memory device may include a semiconductor substrate and an isolation layer on the semiconductor substrate wherein the isolation layer defines an active region of the semiconductor substrate. A tunnel insulation layer may be provided on the active region of the semiconductor substrate, and a charge storage pattern may be provided on the tunnel insulation layer. An interface layer pattern may be provided on the charge storage pattern, and a blocking insulation pattern may be provided on the interface layer pattern. Moreover, the block insulation pattern may include a high-k dielectric material, and the interface layer pattern and the blocking insulation pattern may include different materials. A control gate electrode may be provided on the blocking insulating layer so that the blocking insulation pattern is between the interface layer pattern and the control gate electrode. Related methods are also discussed.
摘要翻译：非易失性存储器件可以包括半导体衬底和半导体衬底上的隔离层，其中隔离层限定半导体衬底的有源区。可以在半导体衬底的有源区上设置隧道绝缘层，并且可以在隧道绝缘层上设置电荷存储图案。可以在电荷存储图案上提供界面层图案，并且可以在界面层图案上提供阻挡绝缘图案。此外，块绝缘图案可以包括高k介电材料，并且界面层图案和阻挡绝缘图案可以包括不同的材料。可以在阻挡绝缘层上设置控制栅电极，使得阻挡绝缘图案位于界面层图案和控制栅电极之间。还讨论了相关方法。

30. 发明授权

US07776687B2 Semiconductor device having a gate contact structure capable of reducing interfacial resistance and method of forming the same 有权
标题翻译：具有能够降低界面电阻的栅极接触结构的半导体器件及其形成方法
公开(公告)号：US07776687B2
公开(公告)日：2010-08-17
申请号：US11797401
申请日：2007-05-03
申请人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
发明人： Chang-Seok Kang , Yoo-Cheol Shin , Jung-Dal Choi , Jong-Sun Sel , Ju-Hyung Kim , Sang-Hun Jeon
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/823462 , H01L21/823475 , H01L27/115 , H01L27/11524 , H01L29/7883
摘要： A semiconductor device has a gate contact structure, including a semiconductor substrate, a polycrystalline silicon layer used as a gate electrode of a transistor, a middle conductive layer, a top metal layer having an opening exposing the polycrystalline silicon layer, and a contact plug directly contacting the polycrystalline silicon layer through the opening.
摘要翻译：半导体器件具有栅极接触结构，包括半导体衬底，用作晶体管的栅电极的多晶硅层，中间导电层，具有暴露多晶硅层的开口的顶部金属层和直接接触的接触插塞使多晶硅层通过开口接触。

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