专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06762957B2 Low clock swing latch for dual-supply voltage design 有权
标题翻译：低电压时钟摆动锁存器用于双电源电压设计
公开(公告)号：US06762957B2
公开(公告)日：2004-07-13
申请号：US10027795
申请日：2001-12-20
申请人： Steven K. Hsu , Bhaskar P. Chatterjee , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Bhaskar P. Chatterjee , Ram K. Krishnamurthy
IPC分类号： G11C710
CPC分类号： H03K3/356139 , H03K3/012
摘要： A dual-supply voltage latch includes a data input node to receive an input data, internal nodes to hold the input data, and an output node to output an output data. The latch also includes clock input nodes to receive a clock signal. The data input, internal, and data output nodes are at a higher potential than the clock nodes. Since clock nodes are high activity nodes, less potential on these nodes reduces the energy consumed by the latch. Although the data nodes and clock nodes are at different potentials, the latch has reduced static power dissipation.
摘要翻译：双电源电压锁存器包括用于接收输入数据的数据输入节点，用于保存输入数据的内部节点以及输出输出数据的输出节点。锁存器还包括时钟输入节点以接收时钟信号。数据输入，内部和数据输出节点处于比时钟节点更高的电位。由于时钟节点是高活动节点，所以这些节点上的较小电位降低了锁存器消耗的能量。虽然数据节点和时钟节点处于不同的电位，但锁存器降低了静态功耗。

22. 发明授权

US06628143B2 Full-swing source-follower leakage tolerant dynamic logic 有权
标题翻译：全摆动源跟踪器泄漏容错动态逻辑
公开(公告)号：US06628143B2
公开(公告)日：2003-09-30
申请号：US09965360
申请日：2001-09-26
申请人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Mark A. Anders , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment of a full-swing, source-follower leakage tolerant dynamic logic gate comprises an nMOSFET logic to conditionally charge a node during an evaluation phase, and to charge the node to a relatively small voltage during the pre-charge phase so that the nMOSFET logic becomes reverse-biased.
摘要翻译：全驱动，源极跟随器泄漏容限动态逻辑门的实施例包括nMOSFET逻辑，用于在评估阶段对节点进行有条件充电，并且在预充电阶段期间将节点充电至相对小的电压，使得nMOSFET 逻辑变为反向偏置。

23. 发明授权

US07332937B2 Dynamic logic with adaptive keeper 有权
标题翻译：动态逻辑与自适应守门员
公开(公告)号：US07332937B2
公开(公告)日：2008-02-19
申请号：US11321328
申请日：2005-12-28
申请人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
IPC分类号： H03K19/096
CPC分类号： H03K19/0963 , G01R31/3008 , G01R31/31721 , H03K19/00361 , H03K19/00384
摘要： Disclosed herein are solutions for providing adaptive keeper functionality to dynamic logic circuits. In some embodiments, a programmable keeper circuit is coupled to a register file circuit. Included is a leakage indicator circuit to model leakage in at least a portion of the register file. A control circuit is coupled to the leakage indicator circuit and to the programmable keeper circuit to control the keeper strength in accordance with the modeled leakage. Other embodiments are claimed or otherwise disclosed.
摘要翻译：这里公开了用于向动态逻辑电路提供自适应保持器功能的解决方案。在一些实施例中，可编程保持器电路耦合到寄存器文件电路。包括泄漏指示器电路，用于在寄存器文件的至少一部分中建模泄漏。控制电路耦合到泄漏指示器电路和可编程保持器电路，以根据建模的泄漏来控制保持器强度。要求保护或以其他方式公开其他实施例。

24. 发明授权

US06404234B1 Variable virtual ground domino logic with leakage control 有权
标题翻译：具有泄漏控制的可变虚拟地面多米诺逻辑
公开(公告)号：US06404234B1
公开(公告)日：2002-06-11
申请号：US09851917
申请日：2001-05-09
申请人： Steven K. Hsu , Sanu K. Mathew , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Sanu K. Mathew , Ram K. Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： A domino logic circuit and method comprise at least two series-connected domino logic stages with each domino logic stage comprising a dynamic stage and a static stage. A variable virtual ground of the first domino logic's static stage is switched to a voltage level below a circuit ground level when a received clock signal and a second domino logic stage's dynamic output are both high, indicating the second domino logic circuit stage is in the evaluation phase.
摘要翻译：多米诺逻辑电路和方法包括至少两个串联连接的多米诺逻辑级，每个多米诺逻辑级包括动态级和静态级。当接收到的时钟信号和第二多米诺逻辑级的动态输出均为高电平时，第一多米诺逻辑逻辑静态级的可变虚拟接地切换到低于电路接地电平的电压电平，表明第二多米诺逻辑电路级处于评估状态相。

25. 发明授权

US07250783B2 Current mirror multi-channel leakage current monitor circuit and method 有权
标题翻译：电流镜多通道漏电流监测电路及方法
公开(公告)号：US07250783B2
公开(公告)日：2007-07-31
申请号：US11022800
申请日：2004-12-28
申请人： Steven K. Hsu , Ram Krishnamurthy , Chris Hyung-il Kim
发明人： Steven K. Hsu , Ram Krishnamurthy , Chris Hyung-il Kim
IPC分类号： G01R31/02
CPC分类号： G11C29/50 , G01R31/3012 , G11C2029/5004 , G11C2029/5006
摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.
摘要翻译：电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。

26. 发明授权

US07016239B2 Leakage tolerant register file 失效
标题翻译：漏电容量寄存器文件
公开(公告)号：US07016239B2
公开(公告)日：2006-03-21
申请号：US10676985
申请日：2003-09-30
申请人： Bhaskar P. Chatterjee , Steven K. Hsu , Sriram R. Vangal , Ram Krishnamurthy
发明人： Bhaskar P. Chatterjee , Steven K. Hsu , Sriram R. Vangal , Ram Krishnamurthy
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C8/10
摘要： A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.
摘要翻译：寄存器文件包含本地位跟踪和驱动信号跟踪以及耦合到本地位跟踪的多个数据单元。一个器件耦合到驱动信号跟踪和本地位跟踪，以智能地对本地位跟踪进行充电和浮动。通过确定数据单元之一的选择来促进智能充电和浮动。

27. 发明授权

US07002375B2 Robust variable keeper strength process-compensated dynamic circuit and method 有权
标题翻译：鲁棒可变门限强度过程补偿动态电路及方法
公开(公告)号：US07002375B2
公开(公告)日：2006-02-21
申请号：US10401774
申请日：2003-03-31
申请人： Steven K. Hsu , Ram Krishnamurthy , Chris Hyung-il Kim
发明人： Steven K. Hsu , Ram Krishnamurthy , Chris Hyung-il Kim
IPC分类号： H03K19/096 , H03K17/16 , H03K19/003
CPC分类号： H03K19/0963
摘要： A variable keeper strength based process-compensated dynamic circuit and method provides a robust digital way to overcome the intrinsic parameter variation present in manufactured die. Using a process-compensated dynamic circuit, the wide robustness and delay distribution becomes narrower which improves performance without sacrificing worst-case robustness. The strength of the keeper is programmed depending on the amount of die leakage. The keeper will have an optimal strength for the best and worst case leakage, allowing better performance with improved worst-case robustness.
摘要翻译：基于可变门限强度的过程补偿动态电路和方法提供了一种鲁棒的数字方式来克服制造的模具中存在的固有参数变化。使用过程补偿动态电路，广泛的鲁棒性和延迟分布变窄，从而提高性能，而不会牺牲最坏情况的鲁棒性。保持器的强度根据模具泄漏量进行编程。守门员将具有最佳和最差情况泄漏的最佳强度，从而改善最坏情况下的鲁棒性。

28. 发明授权

US06628557B2 Leakage-tolerant memory arrangements 有权
标题翻译：防漏记忆布置
公开(公告)号：US06628557B2
公开(公告)日：2003-09-30
申请号：US09966193
申请日：2001-09-28
申请人： Steven K. Hsu , Ram Krishnamurthy
发明人： Steven K. Hsu , Ram Krishnamurthy
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/419
摘要： The present invention is in the area of memory architecture. More particularly, the present invention provides a method, apparatus, machine-readable medium, and system reduce leakage current in memory. Embodiments may take advantage of the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, within the memory to limit leakage and provide for a leakage tolerant data storage technique. Embodiments may also enable the reverse bias characteristic of circuit elements, such as the reverse gate-to-source bias characteristic of a transistor, to be taken advantage of by sourcing charge from data storage elements.
摘要翻译：本发明在存储器架构的领域。更具体地说，本发明提供一种方法，装置，机器可读介质和系统减少存储器中的泄漏电流。实施例可以利用电路元件的反向偏置特性，例如存储器内的晶体管的反向栅极到源极偏置特性，以限制泄漏并提供泄漏容限数据存储技术。实施例还可以使电路元件的反向偏置特性（例如晶体管的反向栅极 - 源极偏置特性）被利用来从数据存储元件中提取电荷。

29. 发明授权

US07362621B2 Register file with a selectable keeper circuit 有权
标题翻译：使用可选保持电路注册文件
公开(公告)号：US07362621B2
公开(公告)日：2008-04-22
申请号：US10676276
申请日：2003-09-30
申请人： Bhaskar P. Chatterjee , Steven K. Hsu , Ram Krishnamurthy
发明人： Bhaskar P. Chatterjee , Steven K. Hsu , Ram Krishnamurthy
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C7/12 , G11C2207/104
摘要： A register file includes a multi-level multiplexer output circuit coupled to a global bit trace and keeper circuitry coupled to said global bit trace and a driving signal trace. The register file also has decoder circuitry coupled to said keeper circuitry to selectively decouple the driving signal trace from said global bit trace.
摘要翻译：寄存器文件包括多电平多路复用器输出电路，其耦合到耦合到所述全局位线跟踪和驱动信号迹线的全局位跟踪和保持器电路。寄存器文件还具有耦合到所述保持器电路的解码器电路，以选择性地将驱动信号迹线与所述全局位线分离。

30. 发明授权

US06693461B2 Multiple supply-voltage zipper CMOS logic family with low active leakage power dissipation 失效
标题翻译：多电源电压拉链CMOS逻辑系列具有低有源漏电功耗
公开(公告)号：US06693461B2
公开(公告)日：2004-02-17
申请号：US10027292
申请日：2001-12-20
申请人： Steven K. Hsu , Ram Krishnamurthy
发明人： Steven K. Hsu , Ram Krishnamurthy
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： An embodiment zipper circuit achieves reduced leakage current by utilizing four voltages so that FETs in the p-logic blocks and n-logic blocks are reversed biased during a pre-charge phase. The FETs in a logic block are also reversed biased during an evaluation phase if the input voltages to the logic block are such that the logic block is not driven ON during the evaluation phase.
摘要翻译：实施例拉链电路通过利用四个电压来实现减小的漏电流，使得在预充电阶段期间p逻辑块和n逻辑块中的FET被反向偏置。如果逻辑块的输入电压使得在评估阶段期间逻辑块不被驱动为ON，则逻辑块中的FET在评估阶段也被反向偏置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式