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21. 发明申请

US20080148088A1 Architecture for a Physical Interface of a High Speed Front Side Bus 失效
标题翻译：高速前端总线物理接口架构
公开(公告)号：US20080148088A1
公开(公告)日：2008-06-19
申请号：US11930345
申请日：2007-10-31
申请人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
发明人： Steven John Baumgartner , Anthony Richard Bonaccio , Timothy Clyde Buchholtz , Daniel Mark Dreps , Charles Porter Geer , Mounir Meghelli , Sergey Vladimirovich Rylov , David W. Siljenberg , Dana Marie Woeste
IPC分类号： G06F11/00
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A design structure for a high speed computer processor system includes a high speed interface for a graphics processor. In a preferred embodiment, the high speed interface includes a front side bus (FSB) that interfaces to a similar high speed interface on the graphics processor.
摘要翻译：用于高速计算机处理器系统的设计结构包括用于图形处理器的高速接口。在优选实施例中，高速接口包括与图形处理器上类似的高速接口相连接的前端总线（FSB）。

22. 发明申请

US20080072093A1 Dynamic Clock Phase Alignment Between Independent Clock Domains 失效
标题翻译：独立时钟域之间的动态时钟相位对准
公开(公告)号：US20080072093A1
公开(公告)日：2008-03-20
申请号：US11870985
申请日：2007-10-11
申请人： Steven John Baumgartner , Charles Porter Geer
发明人： Steven John Baumgartner , Charles Porter Geer
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A design structure is described for dynamically aligning clocks in independent clock domains with minimal latency. In the preferred embodiments, a reference clock in the destination clock domain that is some multiple times the data clock of the destination clock domain is used to sample a data sample signal from the source domain. The sampled data is used to determine at what time slice of the reference clock the data sample signal is changing and therefore at what phase of time slice or phase of the data clock the clocks can be aligned to ensure valid data will be transferred between clock domains.
摘要翻译：描述了一种设计结构，用于以最小的延迟动态地对齐独立时钟域中的时钟。在优选实施例中，目的时钟域中的目的时钟域的数据时钟的多倍的参考时钟用于从源域采样数据采样信号。采样数据用于确定数据采样信号在什么时间片上参考时钟信号正在改变，因此在数据时钟的时间片或相位的什么阶段可以对准时钟，以确保有效数据将在时钟域之间传输。

23. 发明授权

US06870864B2 Optical margin testing system for automatic power control loops 失效
标题翻译：用于自动功率控制回路的光学裕度测试系统
公开(公告)号：US06870864B2
公开(公告)日：2005-03-22
申请号：US10058864
申请日：2002-01-28
申请人： Steven John Baumgartner
发明人： Steven John Baumgartner
IPC分类号： H01S5/00 , H01S5/042 , H01S5/0683 , H01S3/13
CPC分类号： H01S5/042 , H01S5/0014 , H01S5/0683
摘要： An optical margin testing system is provided for automatic power control loops. An optical circuit includes a laser diode and a monitor diode coupled to the automatic power control loop. A bias generator circuit generates a control signal. The control signal is applied to the automatic power control loop. The control signal enables an operation point of the laser diode to both increase and decrease by a set percentage value for optical margin testing. The bias generator circuit includes a tri-state receiver. An input signal is applied to the tri-state receiver for selecting one of a normal operational mode, an increased set percentage value operational mode, and a decreased set percentage value operational mode. A current mirror is coupled to the tri-state receiver provides the control signal that is applied to the automatic power control loop.
摘要翻译：为自动功率控制回路提供光学余量测试系统。光电路包括耦合到自动功率控制回路的激光二极管和监视二极管。偏置发生器电路产生控制信号。控制信号被应用于自动功率控制回路。控制信号使得激光二极管的操作点能够增加和减少用于光学余量测试的设定百分比值。偏置发生器电路包括三态接收器。输入信号被施加到三状态接收器，用于选择正常操作模式，增加的设定百分比值操作模式和减小的设定百分比值操作模式之一。电流镜耦合到三态接收器，提供应用于自动功率控制环路的控制信号。

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