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21. 发明授权

US5885869A Method for uniformly doping hemispherical grain polycrystalline silicon 失效
标题翻译：均匀掺杂半球状晶粒多晶硅的方法
公开(公告)号：US5885869A
公开(公告)日：1999-03-23
申请号：US528183
申请日：1995-09-14
申请人： Charles Turner , Randhir P. S. Thakur
发明人： Charles Turner , Randhir P. S. Thakur
IPC分类号： H01L21/22 , H01L21/02 , H01L21/3215 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/20
CPC分类号： H01L28/84 , H01L21/32155 , H01L27/10808 , H01L29/66181 , Y10S148/014 , Y10S148/122 , Y10S148/138
摘要： A method is disclosed for uniformly doping HSG polycrystalline silicon independent of the other layers of the semiconductor substrate. A semiconductor substrate having a silicon dioxide layer formed superjacent a polysilicon layer is provided in a chamber. A doped rough silicon layer is formed in situ superjacent the silicon dioxide layer. This is accomplished by depositing the silicon layer superjacent the silicon dioxide layer and exposing the silicon layer to a source gas, a dopant gas, and energy, preferably in situ to thereby form uniformly doped silicon layer and roughened polysilicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition.Alternatively, a uniformly doped roughened polysilicon layer is formed superjacent the silicon dioxide layer in situ. This formation is achieved by depositing an amorphous silicon layer superjacent the silicon dioxide layer and roughening the amorphous silicon layer in situ. The step of roughening is achieved by vacuum annealing the amorphous silicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition. The roughened amorphous silicon layer is doped by exposing to a source gas, a dopant gas and energy.
摘要翻译：公开了与半导体衬底的其他层无关的均匀掺杂HSG多晶硅的方法。具有在多晶硅层之上形成的二氧化硅层的半导体衬底设置在室中。掺杂的粗硅层原位形成在二氧化硅层的上方。这是通过沉积超过二氧化硅层的硅层并将硅层暴露于源气体，掺杂剂气体和能量，优选在原位，由此形成均匀掺杂的硅层和使用快速热化学气相沉积的粗糙多晶硅层技术或低压化学气相沉积。或者，原位形成在二氧化硅层之上的均匀掺杂的粗糙多晶硅层。通过沉积位于二氧化硅层之上的非晶硅层并原位粗化非晶硅层来实现该形成。通过使用快速热化学气相沉积技术或低压化学气相沉积对非晶硅层进行真空退火来实现粗糙化的步骤。粗糙化的非晶硅层通过暴露于源气体，掺杂剂气体和能量而被掺杂。

22. 发明授权

US5444013A Method of forming a capacitor 失效
标题翻译：形成电容器的方法
公开(公告)号：US5444013A
公开(公告)日：1995-08-22
申请号：US333262
申请日：1994-11-02
申请人： Salman Akram , Charles Turner , Alan Laulusa
发明人： Salman Akram , Charles Turner , Alan Laulusa
IPC分类号： H01L21/02 , H01L21/311 , H01L21/768 , H01L21/8242
CPC分类号： H01L28/84 , H01L21/31116 , H01L21/76804 , H01L28/82 , H01L28/90 , Y10S148/014 , Y10S148/161 , Y10S148/168 , Y10S438/978
摘要： A method of forming a capacitor includes, a) providing a substrate; b) etching into the substrate to provide a depression in the substrate, the depression having a sidewall which is angled from vertical; c) providing a conformal layer of hemispherical grain polysilicon within the depression and over the angled sidewall, the layer of hemispherical grain polysilicon less than completely filling the depression; and d) ion implanting the hemispherical grain polysilicon layer with a conductivity enhancing impurity. Preferred methods of providing the depression where the substrate comprises SiO.sub.2 include a dry, plasma enhanced, anisotropic spacer etch utilizing reactant gases of CF.sub.4 and CHF.sub.3 provided to the substrate at a volumetric ratio of 1:1, and facet sputter etching.
摘要翻译：一种形成电容器的方法包括：a）提供衬底; b）蚀刻到衬底中以在衬底中提供凹陷，凹陷具有与垂直成一定角度的侧壁; c）在凹陷内和在倾斜的侧壁上提供半球形晶粒多晶硅的保形层，半球形晶粒多晶硅层小于完全填充凹陷; 以及d）离子注入具有导电性增强杂质的半球状晶粒多晶硅层。提供衬底包含SiO 2的凹陷的优选方法包括使用以1:1的体积比提供给衬底的CF 4和CHF 3的反应气体和小面溅射蚀刻的干，等离子体增强的各向异性间隔物蚀刻。

23. 发明授权

US5208479A Method of increasing capacitance of polycrystalline silicon devices by surface roughening and polycrystalline silicon devices 失效
标题翻译：通过表面粗糙化和多晶硅器件增加多晶硅器件电容的方法
公开(公告)号：US5208479A
公开(公告)日：1993-05-04
申请号：US883186
申请日：1992-05-15
申请人： Viju Mathews , Charles Turner
发明人： Viju Mathews , Charles Turner
IPC分类号： H01L21/02 , H01L21/321
CPC分类号： H01L28/84 , H01L21/32105 , Y10S438/923
摘要： A method of forming an electrically conductive polysilicon capacitor plate on a semiconductor substrate includes: a) providing a first layer of conductively doped polysilicon atop a semiconductor substrate to a first selected thickness; b) providing a thin layer of oxide atop the first polysilicon layer to a thickness of from about 2 Angstroms to about 30 Angstroms, the thin oxide layer having an outwardly exposed surface; and c) providing a second layer of conductively doped polysilicon having an outer exposed surface over the outwardly exposed thin oxide surface, the first polysilicon layer being electrically conductive with the second polysilicon layer through the thin layer of oxide, the second polysilicon layer having a second thickness from about 500 Angstroms to about 700 Angstroms, the thin oxide layer reducing silicon atom mobility during polysilicon deposition to induce roughness into the outer exposed polysilicon surface. Preferably, the polysilicon deposition, doping, oxide growth, and subsequent polysilicon deposition is all conducted in a single furnace sequence without removing the wafers from the furnace. Such facilitates throughput, and minimizes exposure of the wafer to handling which could lead to fatal damage. It is also contemplated that selected materials other than oxide would be usable to reduce the surface mobility, and thereby induce roughness. The invention also includes an electrically conductive polysilicon capacitor plate.
摘要翻译：在半导体衬底上形成导电多晶硅电容器板的方法包括：a）在半导体衬底顶部提供第一选择厚度的第一导电掺杂多晶硅层; b）在第一多晶硅层顶部提供厚度为约2埃至约30埃的薄氧化层，所述薄氧化物层具有向外暴露的表面; 以及c）在所述向外暴露的薄氧化物表面上提供具有外部暴露表面的导电掺杂多晶硅的第二层，所述第一多晶硅层通过所述薄层氧化物与所述第二多晶硅层导电，所述第二多晶硅层具有第二厚度从约500埃至约700埃，薄氧化物层降低多晶硅沉积期间的硅原子迁移率，以引起外露多晶硅表面的粗糙度。优选地，多晶硅沉积，掺杂，氧化物生长和随后的多晶硅沉积都在单个炉序列中进行，而不从炉中移除晶片。这有利于吞吐量，并且最小化晶片暴露于处理，这可能导致致命的损坏。还可以想到，除氧化物之外的所选材料可用于降低表面迁移率，从而引起粗糙度。本发明还包括导电多晶硅电容器板。

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