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21. 发明授权

US06455334B1 Probe grid for integrated circuit analysis 失效
标题翻译：探针电网进行集成电路分析
公开(公告)号：US06455334B1
公开(公告)日：2002-09-24
申请号：US09409982
申请日：1999-09-30
申请人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Glen Gilfeather
发明人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Glen Gilfeather
IPC分类号： H01L2166
CPC分类号： G01R31/2884 , Y10S438/977 , Y10S977/854
摘要： The ability to monitor virtually any portion of semiconductor device is enhanced via a grid formed for analyzing circuitry in the semiconductor device. According to an example embodiment of the present invention, a grid having a plurality of narrow probe points is formed extending over target circuitry in a semiconductor device. The grid is accessed and used for monitoring various target circuitry within the device by accessing the part of the grid that corresponds to the portion of the target circuitry to which access is desired.
摘要翻译：通过形成用于分析半导体器件中的电路的栅格来增强对几乎任何部分的半导体器件的监视能力。根据本发明的一个示例性实施例，在半导体器件中形成有延伸超过目标电路的具有多个窄探针点的格栅。电网被访问并用于通过访问对应于期望接入的目标电路的部分的网格部分来监视设备内的各种目标电路。

22. 发明授权

US06417680B1 Method and apparatus for stress testing a semiconductor device using laser-induced circuit excitation 失效
标题翻译：使用激光感应电路激励对半导体器件进行应力测试的方法和装置
公开(公告)号：US06417680B1
公开(公告)日：2002-07-09
申请号：US09408663
申请日：1999-09-29
申请人： Jeffrey D. Birdsley , Rama R. Goruganthu , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
发明人： Jeffrey D. Birdsley , Rama R. Goruganthu , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
IPC分类号： G01R3102
CPC分类号： G01R31/311
摘要： According to an example embodiment, a laser is directed at a target region of a powered semiconductor device via the back side of the device, and active circuitry is selectively excited. In response to the excited circuitry, target circuitry is monitored and a degree of integrity of the operation of the semiconductor device is determined, for example, by detecting the output s/phase characteristics or by monitoring passive emissions from the device. The invention is particularly advantageous in connection with post-manufacture failure analysis.
摘要翻译：根据示例性实施例，激光器经由设备的背面被引导到有源半导体器件的目标区域，并且有选择地激励有源电路。响应于激励电路，监视目标电路，并且例如通过检测输出s /相位特性或通过监视来自装置的被动发射来确定半导体器件的操作的完整程度。本发明在制造后故障分析方面是特别有利的。

23. 发明授权

US06391664B1 Selectively activatable solar cells for integrated circuit analysis 失效
标题翻译：用于集成电路分析的可选活性太阳能电池
公开(公告)号：US06391664B1
公开(公告)日：2002-05-21
申请号：US09409302
申请日：1999-09-29
申请人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
发明人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
IPC分类号： H01L2100
CPC分类号： H01L31/068 , Y02E10/547
摘要： An integrated circuit manufacturing approach involves using a solar cell and facilitating post-manufacturing analysis. According to an example embodiment of the present invention, a solar cell is formed in an integrated circuit device and coupled to target circuitry in the device. The solar cell is activated and provides power to the target circuitry. In response to the solar cell providing power to the target circuitry, the integrated circuit is analyzed.
摘要翻译：集成电路制造方法涉及使用太阳能电池并促进后期制造分析。根据本发明的示例性实施例，太阳能电池形成在集成电路器件中并耦合到器件中的目标电路。太阳能电池被激活并为目标电路提供电力。响应于向目标电路提供电力的太阳能电池，分析集成电路。

24. 发明授权

US06387715B1 Integrated circuit defect detection via laser heat and IR thermography 失效
标题翻译：通过激光热和红外热像仪进行集成电路缺陷检测
公开(公告)号：US06387715B1
公开(公告)日：2002-05-14
申请号：US09409975
申请日：1999-09-30
申请人： Brennan V. Davis , Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Rosalinda M. Ring
发明人： Brennan V. Davis , Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Rosalinda M. Ring
IPC分类号： H01L2166
CPC分类号： H01L22/12 , G01N25/72
摘要： Defect detection for post-manufacturing analysis of an integrated circuit die is enhanced via a method and system that use IR thermography to detect defects in circuitry within the die. According to an example embodiment of the present invention, substrate is removed from an integrated circuit die and a target region is exposed. A portion of the target region is heated with an infrared (IR) laser beam, and the die is imaged using IR thermography. The image is compared with a reference image, and damage to the integrated circuit is detected therefrom.
摘要翻译：通过使用IR热成像技术检测管芯内电路缺陷的方法和系统，增强了集成电路管芯后制造分析的缺陷检测。根据本发明的示例性实施例，从集成电路管芯移除衬底并暴露目标区域。用红外（IR）激光束加热目标区域的一部分，并使用红外热像仪对裸片进行成像。将图像与参考图像进行比较，并从其检测到集成电路的损坏。

25. 发明授权

US06281028B1 LED alignment points for semiconductor die 失效
标题翻译： LED半导体芯片对准点
公开(公告)号：US06281028B1
公开(公告)日：2001-08-28
申请号：US09409087
申请日：1999-09-30
申请人： Michael R. Bruce , Jeffrey D. Birdsley , Rosalinda M. Ring , Rama R. Goruganthu , Brennan V. Davis
发明人： Michael R. Bruce , Jeffrey D. Birdsley , Rosalinda M. Ring , Rama R. Goruganthu , Brennan V. Davis
IPC分类号： H01L2166
CPC分类号： H01L23/544 , H01L2223/54473 , H01L2924/0002 , H01L2924/00
摘要： Post-manufacturing analysis of a semiconductor device is enhanced via a method and system that use a light emitting diode (LED) formed in a semiconductor die during its manufacture. According to an example embodiment of the present invention, a LED is formed within a semiconductor die having a circuit side opposite a back side. A conductor is formed that extends from the LED to the back side of the die, and is coupled to a terminal formed on the back side. The LED is activated via the terminal and used to align the die for analysis. By forming a LED within the semiconductor die during its manufacture, post manufacturing analysis is enhanced by the alignment capabilities provided by the readily activated LED.
摘要翻译：通过在其制造期间使用形成在半导体管芯中的发光二极管（LED）的方法和系统来增强半导体器件的后制造分析。根据本发明的示例性实施例，在具有与背面相对的电路侧的半导体管芯内形成LED。形成从LED延伸到芯片的背面的导体，并且连接到形成在背面的端子。 LED通过端子激活，用于对准芯片进行分析。通过在其制造期间在半导体管芯内形成LED，通过易激活的LED提供的对准能力来增强后制造分析。

26. 发明授权

US06277659B1 Substrate removal using thermal analysis 失效
标题翻译：使用热分析去除基板
公开(公告)号：US06277659B1
公开(公告)日：2001-08-21
申请号：US09409011
申请日：1999-09-29
申请人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
发明人： Rama R. Goruganthu , Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring
IPC分类号： H01L2166
CPC分类号： H01L21/56 , B23K26/034 , B23K26/40 , B23K2101/40 , B23K2103/16 , B23K2103/50 , H01L22/26 , H01L2924/0002 , H01L2924/00
摘要： A substrate removal approach involves sensing acoustic energy in a semiconductor device as a function of substrate thickness in the device as substrate is being removed. According to an example embodiment of the present invention, a semiconductor chip having substrate at a back side that is opposite circuitry at a circuit side is analyzed. Some or all of the substrate in the back side of the semiconductor chip is removed, and a thinned region having a bottom area is formed. A laser is directed to the bottom area, and a thermal parameter characterizing target circuitry in the device is detected in response to the laser. The detected parameter is used and an indication of the remaining substrate thickness between the bottom area and the circuitry is determined. In response to the indicated thickness, the substrate removal process is controlled, making possible effective control of the substrate removal process.
摘要翻译：衬底去除方法包括在衬底被去除的情况下，将器件中的声能作为衬底厚度的函数来检测半导体器件中的声能。根据本发明的示例性实施例，分析了在背面具有与电路侧相对的电路的衬底的半导体芯片。去除半导体芯片的背侧中的一部分或全部基板，形成具有底部区域的变薄区域。激光被引导到底部区域，并且响应于激光器检测表征装置中的目标电路的热参数。使用检测到的参数，并确定底部区域和电路之间的剩余基板厚度的指示。响应于所指示的厚度，控制基板去除过程，使得可以有效地控制基板去除过程。

27. 发明授权

US07019511B1 Optical analysis of integrated circuits 失效
标题翻译：集成电路的光学分析
公开(公告)号：US07019511B1
公开(公告)日：2006-03-28
申请号：US09755008
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M. Ring , Daniel L. Stone
IPC分类号： G01J5/02 , G01R31/00 , G01R31/302
CPC分类号： G01R31/311 , G01N21/1717 , G01N21/9501 , G01N2021/1721 , G01R31/304
摘要： The invention is directed to a system and method for analyzing an integrated circuit having silicon on insulator (SOI) structure. According to one example embodiment of the present invention, an optical beam arrangement is adapted to direct a modulated beam at a selected portion of the integrated circuit. The beam is sufficiently modulated to inhibit optical beam intrusion on the structure and operation of the integrated circuit. A reflected optical waveform response is obtained from the SOI selected portion. The inhibition of optical beam intrusion enhances the ability to analyze integrated circuits using an optical beam, making possible the use of analysis methods that otherwise would be difficult or even impossible to use.
摘要翻译：本发明涉及用于分析具有绝缘体上硅（SOI）结构的集成电路的系统和方法。根据本发明的一个示例性实施例，光束装置适于将调制束指向集成电路的选定部分。光束被充分调制，以阻止光束入射到集成电路的结构和操作上。从SOI选择部分获得反射光波形响应。光束入侵的抑制增强了使用光束分析集成电路的能力，使得可能使用否则将难以甚至不可能使用的分析方法。

28. 发明授权

US06864972B1 IC die analysis via back side lens 失效
标题翻译：通过背面透镜进行IC芯片分析
公开(公告)号：US06864972B1
公开(公告)日：2005-03-08
申请号：US10205766
申请日：2002-07-26
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M Ring , Daniel L. Stone
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Brennan V. Davis , Rosalinda M Ring , Daniel L. Stone
IPC分类号： G01N21/956 , G01N21/88
CPC分类号： G01N21/95684
摘要： The present invention is directed analysis of a flip-chip integrated circuit die having SOI structure that improves the ability to image and analyze selected portions of circuitry in the die. According to an example embodiment of the present invention, a lens is formed in a back side of a flip-chip die and over the insulator portion of SOI structure in the die. Light is directed at the lens and the lens is used to focus the light to target circuitry in the die. A reflection from the circuitry is detected and used to analyze the die, such as by imaging the circuitry in the die and identifying defects therein. The lens formed in the die enhances the ability to focus light to selected circuitry in the die and improves the ability to analyze dies having SOI structure through the insulator.
摘要翻译：本发明是具有SOI结构的倒装芯片集成电路管芯的定向分析，其提高了对管芯中的电路的选定部分进行成像和分析的能力。根据本发明的示例性实施例，透镜形成在倒装芯片的背面中并且在模具中的SOI结构的绝缘体部分上方。光指向透镜，并且透镜用于将光聚焦到模具中的目标电路。检测电路的反射并用于分析管芯，例如通过对管芯中的电路进行成像并识别其中的缺陷。在芯片中形成的透镜增强了将光聚焦到芯片中的所选电路的能力，并提高了通过绝缘体分析具有SOI结构的裸片的能力。

29. 发明授权

US06806166B1 Substrate removal as a function of emitted photons at the back side of a semiconductor chip 有权
标题翻译：作为半导体芯片背面发射的光子的函数的衬底去除
公开(公告)号：US06806166B1
公开(公告)日：2004-10-19
申请号：US09379047
申请日：1999-08-23
申请人： Jeffrey D. Birdsley , Michael R. Bruce , Rama R. Goruganthu , Brennan V. Davis , Rosalinda M. Ring
发明人： Jeffrey D. Birdsley , Michael R. Bruce , Rama R. Goruganthu , Brennan V. Davis , Rosalinda M. Ring
IPC分类号： H01L2130
CPC分类号： H01L22/26
摘要： According to an example embodiment of the present invention, a portion of substrate in the back side of a semiconductor chip is removed as a function of photons emitted through substrate remaining at the back side. The use of emitted photons is used to control the substrate removal process.
摘要翻译：根据本发明的一个示例性实施例，半导体芯片的背面中的基板的一部分作为留在背面的基板发射的光子的函数被去除。使用发射的光子来控制衬底去除过程。

30. 发明授权

US06621281B1 SOI die analysis of circuitry logic states via coupling through the insulator 有权
标题翻译：通过绝缘体耦合的电路逻辑状态的SOI裸片分析
公开(公告)号：US06621281B1
公开(公告)日：2003-09-16
申请号：US09755012
申请日：2001-01-05
申请人： Jeffrey D. Birdsley , Brennan V. Davis , Daniel L. Stone , Michael R. Bruce , Rosalinda M. Ring
发明人： Jeffrey D. Birdsley , Brennan V. Davis , Daniel L. Stone , Michael R. Bruce , Rosalinda M. Ring
IPC分类号： G01R3102
CPC分类号： G01R31/307
摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within die from the back side without breaching the thin insulator layer of the SOI structure. According to an example embodiment, a portion of substrate is removed from the back side of a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side. Electrical connection is made to a portion of the circuitry within the die via a capacitive coupling arrangement. The electrical connection is used to obtain an electrical measurement correlated with circuitry logic states of the die that is used for analysis.
摘要翻译：具有绝缘体上硅（SOI）结构的半导体管芯的分析通过从背面访问管芯内的电路而不破坏SOI结构的薄绝缘体层来增强。根据示例性实施例，从电路侧具有SOI结构和背面相反电路的半导体管芯的背面去除衬底的一部分。通过电容耦合装置对管芯内的电路的一部分进行电连接。电连接用于获得与用于分析的管芯的电路逻辑状态相关的电测量。

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