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21. 发明申请

US20050036388A1 Method and apparatus for increasing data read speed in a semiconductor memory device 有权
标题翻译：用于增加半导体存储器件中的数据读取速度的方法和装置
公开(公告)号：US20050036388A1
公开(公告)日：2005-02-17
申请号：US10915036
申请日：2004-08-10
申请人： Chan-Yong Lee , Jung-Hwa Lee
发明人： Chan-Yong Lee , Jung-Hwa Lee
IPC分类号： G11C11/4091 , G11C5/14 , G11C7/10 , G11C5/00
CPC分类号： G11C7/1069 , G11C5/14 , G11C7/1012 , G11C7/1051
摘要： A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.
摘要翻译：具有数据读取路径的半导体存储器件在数据读取操作期间保持提供给输入/输出读出放大器的输入/输出读出放大器的电压高于提供给数据中的其它电路元件的电压读取路径，从而实现高数据读取速度。

22. 发明授权

US06487132B2 Integrated circuit memory devices having multiple input/output buses and precharge circuitry for precharging the input/output buses between write operations 有权
标题翻译：具有多个输入/输出总线和预充电电路的集成电路存储器件，用于在写入操作之间预充电输入/输出总线
公开(公告)号：US06487132B2
公开(公告)日：2002-11-26
申请号：US09773780
申请日：2001-01-31
申请人： Yong-Cheol Bae , Jung-Hwa Lee
发明人： Yong-Cheol Bae , Jung-Hwa Lee
IPC分类号： G11C700
CPC分类号： G11C7/1006 , G11C7/1048
摘要： Integrated circuit memory devices include precharge controller circuit, which generates a precharge control signal in response to completion of a write operation on a first input/output bus. A precharge circuit drives the first and a input/output buses to a predetermined voltage level in response to the precharge control signal. Multiple switches may be used to couple the first and second input/output buses to the memory cell array and these switches may also be coupled to a column select line. The switches may be responsive to a column select signal carried on the column select line such that one or more memory cells are coupled to the first input/output bus and one or more memory cells are coupled to the second input/output bus simultaneously. Because both of the input/output buses are coupled to the memory cell array in response to the column select signal, the memory cell array may be susceptible to bit line disturbance in which charges remaining on one input/output bus from a previous write operation corrupt memory cells during a write operation on a second input/output bus. By driving the first and second input/output buses to a predetermined voltage level after completing a write operation on one of the two input/output buses, bit line disturbance may be prevented.
摘要翻译：集成电路存储器件包括预充电控制器电路，其响应于在第一输入/输出总线上的写入操作的完成而产生预充电控制信号。预充电电路响应于预充电控制信号将第一输入/输出总线驱动到预定的电压电平。可以使用多个开关将第一和第二输入/输出总线耦合到存储单元阵列，并且这些开关也可以耦合到列选择线。开关可以响应于列选择线上承载的列选择信号，使得一个或多个存储器单元耦合到第一输入/输出总线，并且一个或多个存储器单元同时耦合到第二输入/输出总线。因为响应于列选择信号而将输入/输出总线都耦合到存储单元阵列，所以存储单元阵列可能容易受到位线干扰，其中一个输入/输出总线上剩余的电荷从先前的写操作损坏在第二输入/输出总线上的写操作期间的存储器单元。通过在两个输入/输出总线中的一个完成写入操作之后，通过将第一和第二输入/输出总线驱动到预定的电压电平，可以防止位线干扰。

23. 发明授权

US06215690B1 Semiconductor memory devices having shared data line contacts 有权
标题翻译：具有共享数据线触点的半导体存储器件
公开(公告)号：US06215690B1
公开(公告)日：2001-04-10
申请号：US09536963
申请日：2000-03-28
申请人： Jung-Hwa Lee
发明人： Jung-Hwa Lee
IPC分类号： G11C700
CPC分类号： G11C7/18 , G11C7/1048 , G11C11/4096 , G11C11/4097 , H01L27/10897
摘要： Disclosed herein is a semiconductor memory device which comprises a memory cell array having a plurality of memory cells and a plurality of bit line pairs connected to the memory cells. The device has two data line pairs corresponding to the memory cell array. Furthermore, the device comprises a plurality of selecting transistors connected to the bit line pairs and selecting two bit line pairs to connect the two selected bit line pairs to the two data line pairs in response to a column selection signal. The selecting transistors corresponding to the column selection signal are laid out to share source/drain to data line contacts with contiguous those to be selected by another column selection signal.
摘要翻译：本文公开了一种半导体存储器件，其包括具有多个存储器单元的存储单元阵列和连接到存储器单元的多个位线对。该设备具有对应于存储单元阵列的两条数据线对。此外，该装置包括连接到位线对的多个选择晶体管，并且响应于列选择信号选择两个位线对以将两个所选位线对连接到两个数据线对。对应于列选择信号的选择晶体管布置成将数据线触点与要由另一列选择信号选择的相邻的数据线触点共享。

24. 发明授权

US6023437A Semiconductor memory device capable of reducing a precharge time 有权
标题翻译：能够减少预充电时间的半导体存储器件
公开(公告)号：US6023437A
公开(公告)日：2000-02-08
申请号：US196212
申请日：1998-11-20
申请人： Jung-Hwa Lee
发明人： Jung-Hwa Lee
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401 , G11C7/00
CPC分类号： G11C7/1048
摘要： A high density semiconductor memory device of the present invention provides equalizing circuits for equalizing isolation signals that control a connection between bit lines and sense amplifiers. During a row precharge operation, the equalizing circuits, in response to block selection signals, equalize the isolation signals for transferring signals. As a result, this shortens the required row precharge time.
摘要翻译：本发明的高密度半导体存储器件提供用于均衡用于控制位线和读出放大器之间的连接的隔离信号的均衡电路。在行预充电操作期间，均衡电路响应于块选择信号，均衡用于传送信号的隔离信号。结果，这缩短了所需的行预充电时间。

25. 发明授权

US08475080B2 Method for remediating arsenic-contaminated soil 有权
标题翻译：补救砷污染土壤的方法
公开(公告)号：US08475080B2
公开(公告)日：2013-07-02
申请号：US12940385
申请日：2010-11-05
申请人： Jae-Gon Kim , Jung-Hwa Lee , Yong-Chan Cho , Joo-Sung Ahn , Choon-Oh Lee , Ho-Cheol Song
发明人： Jae-Gon Kim , Jung-Hwa Lee , Yong-Chan Cho , Joo-Sung Ahn , Choon-Oh Lee , Ho-Cheol Song
IPC分类号： B09C1/02
CPC分类号： B09C1/02 , B09C1/08
摘要： Provided is a method for remediating arsenic-contaminated soil, including: a collection step of collecting arsenic-contaminated soil; a washing step of adding the collected soil to a washing solution, which is acidic in nature and provides reducing conditions to the soil, so as to remove arsenic from the soil and transfer the removed arsenic to the washing solution; a solid-liquid separation step of separating the soil and the washing solution from each other after the washing step; and a post-treatment step of removing arsenic from the washing solution, which was separated in the solid-liquid separation step, and employing the soil for remediation.
摘要翻译：提供了一种补救砷污染土壤的方法，包括：收集砷污染土壤的收集步骤; 将收集的土壤添加到本质上是酸性并为土壤提供还原条件的洗涤溶液的洗涤步骤，以从土壤中除去砷并将去除的砷转移到洗涤溶液中; 在洗涤步骤之后将污物和洗涤液彼此分离的固液分离步骤; 以及从固液分离工序中分离的洗涤液中除去砷的后处理工序，并使用土壤进行修复。

26. 发明授权

US07999299B2 Semiconductor memory device having capacitor for peripheral circuit 失效
标题翻译：具有用于外围电路的电容器的半导体存储器件
公开(公告)号：US07999299B2
公开(公告)日：2011-08-16
申请号：US12264490
申请日：2008-11-04
申请人： Jung-Hwa Lee , Si-Woo Lee
发明人： Jung-Hwa Lee , Si-Woo Lee
IPC分类号： H01L27/108
CPC分类号： H01L27/10894 , H01L27/0207 , H01L27/0629 , H01L28/40
摘要： Provided is a semiconductor memory device having peripheral circuit capacitors. In the semiconductor memory device, a first node is electrically connected to a plurality of lower electrodes of a plurality of capacitors in a peripheral circuit region to connect at least a portion of the capacitors in parallel. A second node is electrically connected to a plurality of upper electrodes of the capacitors in the peripheral circuit region to connect at least a portion of the capacitors in parallel. The first node is formed at substantially the same level as a bit line in a cell array region and is formed of the same material used to form the bit line.
摘要翻译：提供了具有外围电路电容器的半导体存储器件。在半导体存储器件中，第一节点电连接到外围电路区域中的多个电容器的多个下电极，以平行地连接至少一部分电容器。第二节点电连接到外围电路区域中的电容器的多个上电极，以平行地连接至少一部分电容器。第一节点形成在与单元阵列区域中的位线基本相同的电平上，并且由用于形成位线的相同材料形成。

27. 发明授权

US07883970B2 Semiconductor device having decoupling capacitor and method of fabricating the same 有权
标题翻译：具有去耦电容器的半导体器件及其制造方法
公开(公告)号：US07883970B2
公开(公告)日：2011-02-08
申请号：US12343035
申请日：2008-12-23
申请人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
发明人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/945 , H01L27/0207 , H01L27/0805 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L29/66181 , H01L29/66621 , H01L29/78
摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.
摘要翻译：提供具有去耦电容器的半导体器件及其制造方法。半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。至少一个通道沟槽设置在半导体衬底的单元区域中。至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。栅电极设置在半导体衬底的单元区域中并填充沟槽。第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。栅极电介质层介于通道沟槽和栅电极之间。在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

28. 发明授权

US07309883B2 Semiconductor device capable of preventing current flow caused by latch-up and method of forming the same 有权
标题翻译：能够防止由闩锁引起的电流的半导体装置及其形成方法
公开(公告)号：US07309883B2
公开(公告)日：2007-12-18
申请号：US10815448
申请日：2004-04-01
申请人： Soon-Hong Ahn , Jung-Hwa Lee
发明人： Soon-Hong Ahn , Jung-Hwa Lee
IPC分类号： H01L29/72
CPC分类号： H01L27/0921 , H01L21/823878 , H01L21/823892
摘要： A semiconductor device includes first, second, and third wells. The first well is connected to a pad to which an external pin is connected and includes a first-type diffusion region that receives a well bias voltage. The second well is adjacent to the first well, and includes an insulating region and a second-type diffusion region outside the insulating region. The third well is adjacent to the second well and includes a first-type diffusion region that receives a first voltage. The insulating region inside the second well along with the first-type well diffusion region of the first well constitute a bipolar junction transistor that cuts off current flowing from the first well to the third well.
摘要翻译：半导体器件包括第一，第二和第三阱。第一阱连接到外部引脚连接到的焊盘，并且包括接收阱偏置电压的第一类型扩散区域。第二阱与第一阱相邻，并且在绝缘区域之外包括绝缘区域和第二类型扩散区域。第三阱与第二阱相邻并且包括接收第一电压的第一类型扩散区域。第二阱内的绝缘区域与第一阱的第一型阱扩散区域一起构成双极结型晶体管，其切断从第一阱流向第三阱的电流。

29. 发明申请

US20070152280A1 Semiconductor memory device with triple well structure and method of manufacturing the same 审中-公开
标题翻译：具有三重阱结构的半导体存储器件及其制造方法
公开(公告)号：US20070152280A1
公开(公告)日：2007-07-05
申请号：US11649774
申请日：2007-01-05
申请人： Jung-Hwa Lee , Jae-Young Lee
发明人： Jung-Hwa Lee , Jae-Young Lee
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/088 , H01L21/761 , H01L21/823493 , H01L27/0928 , H01L27/105 , H01L27/1052
摘要： A semiconductor memory device may include a semiconductor substrate that may have a first conductivity type. A first buried layer may be formed in the semiconductor substrate and may have a second conductivity type opposite to the first type conductivity. A first well may be formed on the first buried layer and may have the first type conductivity. A second well may be formed in the first well over a first surface portion of the first buried layer and may have the second conductivity type. A second buried layer may be formed in the first well and on a second surface portion of the first buried layer and may have the first conductivity type. A third well may be formed in the first well and on the second buried layer and may have the second conductivity type.
摘要翻译：半导体存储器件可以包括可以具有第一导电类型的半导体衬底。可以在半导体衬底中形成第一掩埋层，并且可以具有与第一类型导电性相反的第二导电类型。第一阱可以形成在第一掩埋层上并且可以具有第一类型的导电性。可以在第一阱中的第一掩埋层的第一表面部分上形成第二阱，并且可以具有第二导电类型。可以在第一阱中和第一掩埋层的第二表面部分上形成第二掩埋层，并且可以具有第一导电类型。可以在第一阱和第二掩埋层中形成第三阱，并且可以具有第二导电类型。

30. 发明申请

US20070052013A1 Semiconductor device having decoupling capacitor and method of fabricating the same 失效
标题翻译：具有去耦电容器的半导体器件及其制造方法
公开(公告)号：US20070052013A1
公开(公告)日：2007-03-08
申请号：US11449959
申请日：2006-06-09
申请人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
发明人： Hyun-Ki Kim , Jung-Hwa Lee , Ji-Young Kim
IPC分类号： H01L29/94
CPC分类号： H01L29/945 , H01L27/0207 , H01L27/0805 , H01L27/10861 , H01L27/10876 , H01L27/10894 , H01L29/66181 , H01L29/66621 , H01L29/78
摘要： A semiconductor device having a decoupling capacitor and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate having a cell region, a first peripheral circuit region, and a second peripheral circuit region. At least one channel trench is disposed in the cell region of the semiconductor substrate. At least one first capacitor trench is disposed in the first peripheral circuit region of the semiconductor substrate, and at least one second capacitor trench is disposed in the second peripheral circuit region of the semiconductor substrate. A gate electrode is disposed in the cell region of the semiconductor substrate and fills the channel trench. A first upper electrode is disposed in the first peripheral circuit region of the semiconductor substrate and fills at least the first capacitor trench. A second upper electrode is disposed in the second peripheral circuit region of the semiconductor substrate and fills at least the second capacitor trench. A gate dielectric layer is interposed between the channel trench and the gate electrode. A first dielectric layer is interposed between the semiconductor substrate of the first peripheral circuit region having the first capacitor trench and the first upper electrode and has the same thickness as the gate dielectric layer. A second dielectric layer is interposed between the semiconductor substrate of the second peripheral circuit region having the second capacitor trench and the second upper electrode and has a different thickness from the first dielectric layer.
摘要翻译：提供具有去耦电容器的半导体器件及其制造方法。半导体器件包括具有单元区域，第一外围电路区域和第二外围电路区域的半导体衬底。至少一个通道沟槽设置在半导体衬底的单元区域中。至少一个第一电容器沟槽设置在半导体衬底的第一外围电路区域中，并且至少一个第二电容器沟槽设置在半导体衬底的第二外围电路区域中。栅电极设置在半导体衬底的单元区域中并填充沟槽。第一上电极设置在半导体衬底的第一外围电路区域中，并且填充至少第一电容器沟槽。第二上电极设置在半导体衬底的第二外围电路区域中，并且填充至少第二电容器沟槽。栅极电介质层介于通道沟槽和栅电极之间。在具有第一电容器沟槽的第一外围电路区域的半导体衬底和第一上电极之间插入第一电介质层，并且具有与栅极电介质层相同的厚度。在具有第二电容器沟槽的第二外围电路区域的半导体衬底和第二上部电极之间插入第二电介质层，并且具有与第一电介质层不同的厚度。

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