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21. 发明授权

US08154539B2 Drive circuit, display apparatus using drive circuit, and evaluation method of drive circuit 失效
公开(公告)号：US08154539B2
公开(公告)日：2012-04-10
申请号：US12042459
申请日：2008-03-05
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： G09G5/00 , G06F3/038
CPC分类号： G09G3/3283 , G09G3/006 , G09G3/325 , G09G2300/0842 , G09G2300/0861 , G09G2320/029 , G09G2320/043
摘要： For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits are commonly connected, a correction value output circuit for outputting a correction value obtained by evaluating the output of one or more specific circuits of the plurality of current signal generation circuits on a basis of current values output through the current signal output line, and a correction circuit for correcting an image signal supplied to the current signal generation circuits by means of the correction value.

22. 发明授权

US07911425B2 Display device 有权
标题翻译：显示设备
公开(公告)号：US07911425B2
公开(公告)日：2011-03-22
申请号：US11917068
申请日：2007-03-30
申请人： Tatsuhito Goden , Somei Kawasaki , Masami Iseki
发明人： Tatsuhito Goden , Somei Kawasaki , Masami Iseki
IPC分类号： G09G3/30
CPC分类号： G09G3/3233 , G09G3/2014 , G09G3/3266 , G09G2300/0842 , G09G2300/0861 , G09G2310/0205 , G09G2310/0224 , G09G2320/0247
摘要： In a current driving display device, a first operation in which pixel circuits in odd rows are sequentially scanned to set a current supplied to display elements and a second operation in which pixel circuits in even rows are sequentially scanned to set a current supplied to display elements are alternately repeated. The current set in the pixel circuits is supplied to the display elements in parallel with the first and second operations, and the number of times in the period is twice or more than the number of times in which the pixel circuit sets a current supplied to the display element.
摘要翻译：在当前驱动显示装置中，顺序地扫描奇数行中的像素电路以设置提供给显示元件的电流的第一操作和顺序地扫描偶数行的像素电路以设置提供给显示元件的电流的第二操作交替重复。像素电路中设置的电流与第一和第二操作并行地提供给显示元件，并且周期中的次数是两倍或更多次，其中像素电路将提供给显示元素。

23. 发明申请

US20100026677A1 DISPLAY APPARATUS AND ELECTRONIC DEVICE USING THE SAME 有权
标题翻译：显示装置和使用该显示装置的电子装置
公开(公告)号：US20100026677A1
公开(公告)日：2010-02-04
申请号：US12444082
申请日：2008-06-17
申请人： Noriyuki Shikina , Hideo Mori , Tatsuhito Goden , Somei Kawasaki , Masami Iseki
发明人： Noriyuki Shikina , Hideo Mori , Tatsuhito Goden , Somei Kawasaki , Masami Iseki
IPC分类号： G06F3/038
CPC分类号： G09G3/325 , G09G3/3266 , G09G2300/0842 , G09G2300/0861 , G09G2320/0247
摘要： A display apparatus includes two-dimensionally arranged light emitting devices driven by drive circuits, scanning lines and lighting lines connecting the drive circuits in a row direction, and data lines connecting the drive circuits in a column direction, wherein, in a programming scanning period for supplying signals to the data lines, sequentially selecting the scanning lines and setting the signals to the drive circuits connected to the selected scanning lines throughout all scanning lines, the light emitting scanning for sequentially selecting the lighting lines and supplying current corresponding to the signal set to the drive circuits from the drive circuit connected to the selected lighting lines to the light emitting device is performed at least twice, and the length of a period for supplying the currents from the drive circuits connected to the lighting lines to the light emitting devices varies every period of the light emitting scanning.
摘要翻译：一种显示装置，包括由行方向驱动电路，扫描线和连接驱动电路的点亮线以及沿列方向连接驱动电路的数据线驱动的二维布置的发光装置，其中，在编程扫描期间，向数据线提供信号，顺序地选择扫描线并将信号设置到连接到所有扫描线上的所选择的扫描线的驱动电路，发光扫描用于顺序地选择照明线并将与该信号相对应的电流设置为连接到所选择的发光线路的驱动电路到发光器件的驱动电路至少执行两次，并且用于将连接到照明线路的驱动电路的电流供应到发光器件的周期的长度每个发光扫描周期。

24. 发明申请

US20090109144A1 CIRCUIT DEVICE AND ACTIVE-MATRIX DISPLAY APPARATUS 失效
标题翻译：电路设备和主动矩阵显示设备
公开(公告)号：US20090109144A1
公开(公告)日：2009-04-30
申请号：US12256919
申请日：2008-10-23
申请人： Tatsuhito Goden , Somei Kawasaki , Masami Iseki
发明人： Tatsuhito Goden , Somei Kawasaki , Masami Iseki
IPC分类号： G09G3/30 , G09G3/36
CPC分类号： G09G3/3283 , G09G3/3225 , G09G2300/0426 , G09G2310/0297 , G09G2320/0209 , G09G2320/0233
摘要： A circuit device includes a first circuit including a thin-film transistor and a second circuit including another thin-film transistor. The second circuit is controlled by control signals including a first control signal and a second control signal delayed from the first control signal. The second control signal is generated on the basis of the first control signal which has been propagated through the second circuit.
摘要翻译：电路装置包括包括薄膜晶体管的第一电路和包括另一薄膜晶体管的第二电路。第二电路由包括第一控制信号和从第一控制信号延迟的第二控制信号的控制信号控制。基于已通过第二电路传播的第一控制信号产生第二控制信号。

25. 发明申请

US20060132395A1 Current Programming Apparatus, Matrix Display Apparatus and Current Programming Method 有权
标题翻译：当前编程设备，矩阵显示设备和当前编程方法
公开(公告)号：US20060132395A1
公开(公告)日：2006-06-22
申请号：US11275011
申请日：2005-12-01
申请人： Somei Kawasaki , Masami Iseki , Fujio Kawano , Takanori Yamashita
发明人： Somei Kawasaki , Masami Iseki , Fujio Kawano , Takanori Yamashita
IPC分类号： G09G3/22
CPC分类号： G09G3/3283 , G09G3/325 , G09G2300/0426 , G09G2300/0861 , G09G2310/0251 , G09G2320/0223
摘要： A current programming apparatus having two data lines for a pixel line is presented. An image data current is supplied to the first and the second data lines alternatively by switching M1 and M2 complementally. By switching M7 and M8 on during the switches M1 and M2 turn on respectively, a constant current is supplied to the data line to which the data current is not supplied. The scanning signals are applied so as to write a constant current into pixels immediately before the data current is written. Thus a write-in defect by a fluctuation in the threshold voltages is prevented.
摘要翻译：提出了一种具有用于像素线的两条数据线的当前编程设备。通过互补地切换M 1和M 2，将图像数据电流交替地提供给第一和第二数据线。通过在开关M 1和M 2分别导通时切换M 7和M 8导通，向不提供数据电流的数据线提供恒定电流。施加扫描信号，以便在写入数据电流之前将恒定电流写入像素。因此，防止了由阈值电压的波动引起的写入缺陷。

26. 发明申请

US20060061403A1 Input circuit, display device and information display apparatus 有权
公开(公告)号：US20060061403A1
公开(公告)日：2006-03-23
申请号：US11219730
申请日：2005-09-07
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： H03L5/00
CPC分类号： G09G3/3233 , G09G3/3241 , G09G3/325 , G09G3/3283 , G09G3/3291 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/027 , G09G2310/0289 , G09G2310/066 , G09G2320/0238 , G09G2320/0252 , G09G2320/0276 , G09G2320/043 , G09G2330/021 , H03K3/356113 , H03K3/356165 , H03K19/018571
摘要： A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.

27. 发明授权

US06914956B2 Shift register, display apparatus and information display apparatus 失效
标题翻译：移位寄存器，显示装置和信息显示装置
公开(公告)号：US06914956B2
公开(公告)日：2005-07-05
申请号：US10650731
申请日：2003-08-29
申请人： Somei Kawasaki , Masami Iseki
发明人： Somei Kawasaki , Masami Iseki
IPC分类号： H01L51/50 , G09G3/20 , G09G3/30 , G09G3/36 , G11C19/00 , G11C19/18 , G11C19/28
CPC分类号： G11C19/00 , G11C19/184
摘要： A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied. During the first period in which the clock signal is supplied, a status signal is inputted from the earlier shift pulse generation unit, and a status signal is not inputted from the later shift pulse generation unit.
摘要翻译：移位寄存器包括多个脉冲产生部分，用于响应输入的时钟信号的电平变化和多个移位脉冲产生单元产生一系列脉冲信号。多个移位脉冲发生单元具有预定的移位脉冲生成单元，其中，所述预定移位脉冲发生单元具有状态信号生成电路，用于将第一状态信号输出到与之前的移位脉冲发生单元连接有移位脉冲发生单元，以及时钟提供电路，用于向属于预定移位脉冲发生单元的脉冲发生部分提供时钟信号。此外，存在第一时段，其中时钟供给电路将时钟信号提供给属于预定移位脉冲产生单元的脉冲产生部分和不提供时钟信号的第二周期。在提供时钟信号的第一时段期间，从较早的移位脉冲发生单元输入状态信号，并且不从后面的移位脉冲产生单元输入状态信号。

28. 发明申请

US20050141665A1 Shift register, display apparatus and information display apparatus 有权
公开(公告)号：US20050141665A1
公开(公告)日：2005-06-30
申请号：US11051187
申请日：2005-02-07
申请人： Somei Kawasaki , Masami Iseki
发明人： Somei Kawasaki , Masami Iseki
IPC分类号： H01L51/50 , G09G3/20 , G09G3/30 , G09G3/36 , G11C19/00 , G11C19/18 , G11C19/28
CPC分类号： G11C19/00 , G11C19/184
摘要： A shift register includes a plurality of pulse generation portions for generating a series of pulse signals in response to a level change of inputted clock signals, and a plurality of shift pulse generation units. The plurality of shift pulse generation units has a predetermined shift pulse generation unit, with the predetermined shift pulse generation unit having a status signal generation circuit for outputting a first status signal to common wiring to which both of an earlier shift pulse generation unit and a later shift pulse generation unit are connected, and a clock supply circuit for supplying a clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit. In addition, there is a first period in which the clock supply circuit supplies the clock signal to the pulse generation portion which belongs to the predetermined shift pulse generation unit and a second period in which the clock signal is not supplied. During the first period in which the clock signal is supplied, a status signal is inputted from the earlier shift pulse generation unit, and a status signal is not inputted from the later shift pulse generation unit.

29. 发明申请

US20050030070A1 Input circuit, display device and information display apparatus 失效
标题翻译：输入电路，显示装置及信息显示装置
公开(公告)号：US20050030070A1
公开(公告)日：2005-02-10
申请号：US10938838
申请日：2004-09-13
申请人： Somei Kawasaki , Fujio Kawano , Masami Iseki
发明人： Somei Kawasaki , Fujio Kawano , Masami Iseki
IPC分类号： H01L51/50 , G09G3/20 , G09G3/30 , G09G3/32 , H03F3/45 , H03K19/0185 , H03B1/00
CPC分类号： G09G3/3233 , G09G3/3241 , G09G3/325 , G09G3/3283 , G09G3/3291 , G09G2300/0819 , G09G2300/0842 , G09G2300/0852 , G09G2300/0861 , G09G2310/027 , G09G2310/0289 , G09G2310/066 , G09G2320/0238 , G09G2320/0252 , G09G2320/0276 , G09G2320/043 , G09G2330/021 , H03K3/356113 , H03K3/356165 , H03K19/018571
摘要： A first current mirror circuit performs its normal operation when a first switch is turned on, and is constructed so that a period during which the first current mirror circuit can output a current is realized when the first switch is turned off. A second current mirror circuit is connected to the first current mirror circuit so that the output current of the first current mirror circuit is decreased by an output current of the second current mirror circuit. A current output of a transistor and a current output of the first current mirror circuit are connected and outputted as an output signal. The first switch and a second switch are controlled by the output signal or a signal formed by the output signal being passed through a buffer circuit.
摘要翻译：当第一开关导通时，第一电流镜电路执行其正常操作，并且被构造成使得当第一开关断开时可以实现第一电流镜电路输出电流的时段。第二电流镜电路连接到第一电流镜电路，使得第一电流镜电路的输出电流由第二电流镜电路的输出电流减小。晶体管的电流输出和第一电流镜电路的电流输出被连接并作为输出信号输出。第一开关和第二开关由输出信号或由输出信号形成的信号通过缓冲电路控制。

30. 发明授权

US5825939A Pixel modulation circuit and recording apparatus using the same 失效
标题翻译：像素调制电路及使用其的记录装置
公开(公告)号：US5825939A
公开(公告)日：1998-10-20
申请号：US628001
申请日：1996-04-04
申请人： Somei Kawasaki , Masami Iseki , Hironari Ebata
发明人： Somei Kawasaki , Masami Iseki , Hironari Ebata
IPC分类号： G06K15/12 , G06K9/38
CPC分类号： G06K15/1223
摘要： A pixel modulation circuit outputs a pulse signal having a pulse width corresponding to pixel data representing a gradation level of each pixel. The pixel modulation circuit comprises a first triangular pulse generating circuit for generating a periodic triangular pulse signal, a complement and antilog output circuit capable of outputting a level signal corresponding to both antilog and complement values of pixel data, and a comparison circuit for comparing the triangular pulse signal with the level signal.
摘要翻译：像素调制电路输出具有与表示各像素的灰度等级的像素数据对应的脉冲宽度的脉冲信号。像素调制电路包括用于产生周期性三角形脉冲信号的第一三角形脉冲发生电路，能够输出对应于像素数据的对数和补码的电平信号的补码和反逻辑输出电路，以及比较电路，脉冲信号与电平信号。

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