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21. 发明授权

US08450783B2 Semiconductor device 有权
公开(公告)号：US08450783B2
公开(公告)日：2013-05-28
申请号：US12978805
申请日：2010-12-27
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
IPC分类号： H01L27/085
CPC分类号： H01L29/7869 , G11C16/0425 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/1156 , H01L27/11563 , H01L27/11568 , H01L27/1225 , H01L28/40 , H01L29/78693 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.

22. 发明授权

US08422272B2 Semiconductor device and driving method thereof 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08422272B2
公开(公告)日：2013-04-16
申请号：US13195105
申请日：2011-08-01
申请人： Hiroki Inoue , Kiyoshi Kato , Takanori Matsuzaki , Shuhei Nagatsuka
发明人： Hiroki Inoue , Kiyoshi Kato , Takanori Matsuzaki , Shuhei Nagatsuka
IPC分类号： G11C11/24
CPC分类号： H01L27/1052 , G11C11/404 , G11C11/405 , G11C11/4091 , G11C16/0408 , G11C16/08 , G11C16/24 , H01L21/02565 , H01L21/02631 , H01L21/425 , H01L21/441 , H01L21/477 , H01L27/108 , H01L27/11521 , H01L27/11526 , H01L27/1156 , H01L27/1207 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/66969 , H01L29/78651 , H01L29/7869 , H01L29/78696
摘要： A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
摘要翻译：提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。

23. 发明授权

US08320162B2 Semiconductor device and driving method of the same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US08320162B2
公开(公告)日：2012-11-27
申请号：US13022407
申请日：2011-02-07
申请人： Hiroki Inoue , Kiyoshi Kato , Takanori Matsuzaki , Shuhei Nagatsuka
发明人： Hiroki Inoue , Kiyoshi Kato , Takanori Matsuzaki , Shuhei Nagatsuka
IPC分类号： G11C11/24
CPC分类号： G11C11/24 , G11C11/403 , G11C11/405 , H01L27/1052 , H01L27/11521 , H01L27/1225
摘要： An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.
摘要翻译：目的在于提供具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且写入的次数不受限制。半导体器件使用宽间隙半导体形成，并且包括电位改变电路，其选择性地将与位线的电位等于或不同的电位施加到源极线。因此，可以充分降低半导体器件的功耗。

24. 发明申请

US20120012845A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120012845A1
公开(公告)日：2012-01-19
申请号：US13182488
申请日：2011-07-14
申请人： Kiyoshi Kato , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
发明人： Kiyoshi Kato , Takanori Matsuzaki , Shuhei Nagatsuka , Hiroki Inoue
IPC分类号： H01L27/108
CPC分类号： H01L27/11517 , G11C16/0433 , G11C16/26 , H01L27/1156 , H01L29/78
摘要： A semiconductor device with a novel structure is provided, which can hold stored data even when no power is supplied and which has no limitations on the number of writing operations. A semiconductor device is formed using a material which enables off-state current of a transistor to be reduced significantly; e.g., an oxide semiconductor material which is a wide-gap semiconductor. With use of a semiconductor material which enables off-state current of a transistor to be reduced significantly, the semiconductor device can hold data for a long period. In a semiconductor device with a memory cell array, parasitic capacitances generated in the nodes of the first to the m-th memory cells connected in series are substantially equal, whereby the semiconductor device can operate stably.
摘要翻译：提供具有新颖结构的半导体器件，其即使在没有供电的情况下也可以保存存储的数据，并且对写入操作的数量没有限制。使用能够显着降低晶体管的截止电流的材料形成半导体器件; 例如，作为宽间隙半导体的氧化物半导体材料。通过使用能够显着降低晶体管的截止电流的半导体材料，半导体器件可以长期保存数据。在具有存储单元阵列的半导体器件中，在串联连接的第一至第m存储器单元的节点中产生的寄生电容基本相等，由此半导体器件可以稳定地工作。

25. 发明申请

US20110156028A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110156028A1
公开(公告)日：2011-06-30
申请号：US12978805
申请日：2010-12-27
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
IPC分类号： H01L27/108
CPC分类号： H01L29/7869 , G11C16/0425 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/1156 , H01L27/11563 , H01L27/11568 , H01L27/1225 , H01L28/40 , H01L29/78693 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
摘要翻译：半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。第二晶体管包括氧化物半导体材料。

26. 发明授权

US08456148B2 Regulator circuit and RFID tag including the same in wireless communication to improve noise margin 有权
公开(公告)号：US08456148B2
公开(公告)日：2013-06-04
申请号：US12686579
申请日：2010-01-13
申请人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
发明人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
IPC分类号： G05F3/16 , G05F1/00
摘要： One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

27. 发明申请

US20100181985A1 Regulator Circuit and RFID Tag Including the Same 有权
标题翻译：调节器电路和包括它的RFID标签
公开(公告)号：US20100181985A1
公开(公告)日：2010-07-22
申请号：US12686579
申请日：2010-01-13
申请人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
发明人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
IPC分类号： G05F3/16
CPC分类号： G05F3/16 , G05F1/56 , G05F3/242
摘要： One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
摘要翻译：本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。

28. 发明授权

US08587286B2 Regulator circuit and RFID tag including the same in wireless communication to improve noise margin 有权
标题翻译：调节器电路和RFID标签在无线通信中包括相同，以提高噪声容限
公开(公告)号：US08587286B2
公开(公告)日：2013-11-19
申请号：US12686579
申请日：2010-01-13
申请人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
发明人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
IPC分类号： G05F3/16 , G05F1/00
CPC分类号： G05F3/16 , G05F1/56 , G05F3/242
摘要： One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
摘要翻译：本发明的一个目的是提供一种具有改善的噪声容限的调节器电路。在包括基于第一电源端子和第二电源端子之间的电位差产生参考电压的偏置电路的调节器电路中，以及基于参考电位向输出端子输出电位的电压调节器在偏置电路的输入端，在电源端子与偏置电路中包含的晶体管的栅极连接的节点之间设置有旁路电容器。

29. 发明授权

US08344719B2 Regulator circuit and RFID tag including the same in wireless communication to improve noise margin 有权
公开(公告)号：US08344719B2
公开(公告)日：2013-01-01
申请号：US12686579
申请日：2010-01-13
申请人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
发明人： Hiroki Inoue , Kiyoshi Kato , Shuhei Nagatsuka , Koichiro Kamata , Tsutomu Murakawa , Takahiro Tuji , Kaori Ikada
IPC分类号： G05F3/16 , G05F1/00
摘要： One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.

30. 发明申请

US20120012837A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120012837A1
公开(公告)日：2012-01-19
申请号：US13175542
申请日：2011-07-01
申请人： Shunpei Yamazaki , Kiyoshi Kato , Shuhei Nagatsuka
发明人： Shunpei Yamazaki , Kiyoshi Kato , Shuhei Nagatsuka
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , G11C16/0433 , G11C16/26 , H01L27/11517 , H01L27/1156 , H01L27/1211 , H01L27/1225
摘要： A semiconductor device with a novel structure in which stored data can be retained even when power is not supplied, and does not have a limitation on the number of write cycles. The semiconductor device includes a memory cell including a first transistor, a second transistor, and an insulating layer placed between a source region or a drain region of the first transistor and a channel formation region of the second transistor. The first transistor and the second transistor are provided to at least partly overlap with each other. The insulating layer and a gate insulating layer of the second transistor satisfy the following formula: (ta/tb)×(εra/εrb)
摘要翻译：具有新颖结构的半导体器件，其中即使在未提供电力的情况下也可以保留存储的数据，并且对写入周期的数量没有限制。半导体器件包括存储单元，其包括第一晶体管，第二晶体管和放置在第一晶体管的源极区域或漏极区域与第二晶体管的沟道形成区域之间的绝缘层。第一晶体管和第二晶体管被设置为至少部分地彼此重叠。第二晶体管的绝缘层和栅极绝缘层满足下式：（ta / tb）×（＆egr; rb /＆egr; ra）<0.1，其中，ta表示栅极绝缘层的厚度，tb表示厚度绝缘层的介电常数表示绝缘层的介电常数，rb表示绝缘层的介电常数。

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