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    • 21. 发明授权
    • Semiconductor integrated circuit device for driving a magnetic disk apparatus
    • 用于驱动磁盘装置的半导体集成电路装置
    • US06268763B1
    • 2001-07-31
    • US09249120
    • 1999-02-12
    • Akio Fujikawa
    • Akio Fujikawa
    • G05F110
    • G11B5/012
    • A semiconductor integrated circuit device for a magnetic disk apparatus has analog circuits such as a read/write circuit and digital circuits such as an interface driver circuit, a control circuit, and a stepping motor driver circuit, all of these circuits operating on a single supply voltage. The semiconductor integrated circuit device further has a voltage regulator whose output voltage is lower than the supply voltage and variable according to the voltage applied to an output voltage adjustment terminal. The control circuit operates on the output voltage of this regulator.
    • 一种用于磁盘装置的半导体集成电路装置具有诸如读/写电路和诸如接口驱动电路,控制电路和步进电机驱动电路的数字电路的模拟电路,所有这些电路都在单个电源 电压。 半导体集成电路装置还具有输出电压低于电源电压并根据施加到输出电压调整端子的电压而变化的电压调节器。 控制电路对该稳压器的输出电压进行工作。
    • 22. 发明授权
    • Frequency and phase comparator
    • 频率和相位比较器
    • US5631582A
    • 1997-05-20
    • US508884
    • 1995-07-28
    • Akio Fujikawa
    • Akio Fujikawa
    • G01R23/00G01R25/00H03D13/00
    • G01R23/005G01R25/005H03D13/004
    • A frequency and phase comparator has a first flip-flop and a second flip-flop. Logical calculation between the outputs of these flip-flops is performed by an AND circuit, and the first and second flip-flops are reset by the output of the logical calculation. The first and second flip-flops receive periodic signals at their clock terminals. When the periods of the output pulses of the first and second flip-flops are short, a circuit driven by the pulses sometimes cannot operate correctly. To prevent this, a pulse generating circuit is provided which receives a first periodic signal and a second periodic signal to generate a pulse signal of a predetermined width, and the pulse signal is added to the outputs of the first and second flip-flops.
    • 频率和相位比较器具有第一触发器和第二触发器。 这些触发器的输出之间的逻辑运算由AND电路执行,第一和第二触发器由逻辑运算的输出复位。 第一和第二触发器在其时钟端子处接收周期性信号。 当第一和第二触发器的输出脉冲的周期短时,由脉冲驱动的电路有时不能正确地操作。 为了防止这种情况,提供脉冲发生电路,其接收第一周期信号和第二周期信号以产生预定宽度的脉冲信号,并且将脉冲信号相加到第一和第二触发器的输出。