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21. 发明授权

US08836903B2 Liquid crystal display 有权
标题翻译：液晶显示器
公开(公告)号：US08836903B2
公开(公告)日：2014-09-16
申请号：US12900436
申请日：2010-10-07
申请人： Se-Hyoung Cho , Dong-Gyu Kim , Mee-Hye Jung , Dong-Hyeon Ki , Seung-Soo Baek , Hye-Seok Na
发明人： Se-Hyoung Cho , Dong-Gyu Kim , Mee-Hye Jung , Dong-Hyeon Ki , Seung-Soo Baek , Hye-Seok Na
IPC分类号： G02F1/1343 , G02F1/139 , G09G3/36 , G02F1/1362
CPC分类号： G02F1/1395 , G02F1/134363 , G02F1/136213 , G09G3/3648 , G09G2300/0426 , G09G2300/043 , G09G2300/0443 , G09G2300/0447
摘要： A liquid crystal display includes first and second substrates, and a liquid crystal layer disposed therebetween. First and second gate lines are disposed on the first substrate. First and second data lines, and a power line are disposed on the first substrate. A first switching element is connected to the first gate line and the first data line, a second switching element is connected to the first gate line and the power line, a third switching element is connected to the second gate line and the second data line, a first pixel electrode is connected to the first switching element, a second pixel electrode is connected to the second switching element, a third pixel electrode is connected to the second switching element, and a fourth pixel electrode is connected to the third switching element, and a gate-on voltage can be simultaneously applied to the first and second gate lines.
摘要翻译：液晶显示器包括第一和第二基板以及设置在其间的液晶层。第一和第二栅极线设置在第一基板上。第一和第二数据线，以及电源线设置在第一基板上。第一开关元件连接到第一栅极线和第一数据线，第二开关元件连接到第一栅极线和电源线，第三开关元件连接到第二栅极线和第二数据线，第一像素电极连接到第一开关元件，第二像素电极连接到第二开关元件，第三像素电极连接到第二开关元件，第四像素电极连接到第三开关元件，以及栅极导通电压可以同时施加到第一和第二栅极线。

22. 发明授权

US08018542B2 Display substrate for easy detection of pattern misalignment 有权
标题翻译：显示基板，便于检测图案不对准
公开(公告)号：US08018542B2
公开(公告)日：2011-09-13
申请号：US11502915
申请日：2006-08-10
申请人： Jung-Joon Park , Min-Wook Park , Dong-Hyeon Ki
发明人： Jung-Joon Park , Min-Wook Park , Dong-Hyeon Ki
IPC分类号： G02F1/1333
CPC分类号： G02F1/136259 , G02F2001/136254
摘要： A display substrate includes a base substrate, a conductive line on the base substrate, a switching element and a testing member. The switching element includes a first electrode formed on the semiconductor layer pattern and electrically connected to the conductive line, and a second electrode spaced apart from the first electrode and semiconductor layer pattern. The testing member includes a conductive line testing portion that is formed from the same layer as the conductive line and an electrode testing portion that is formed from the same layer as the first electrode. The conductive line testing portion and the electrode testing portion have substantially the same width as the conductive line and the first electrode, respectively. The testing member also includes a semiconductor layer testing portion. The display substrate lends itself to efficient manufacturing with reduced process time and cost.
摘要翻译：显示基板包括基底基板，基底基板上的导线，开关元件和测试部件。开关元件包括形成在半导体层图案上并电连接到导电线的第一电极和与第一电极和半导体层图案间隔开的第二电极。测试构件包括由与导电线相同的层形成的导线测试部分和由与第一电极相同的层形成的电极测试部分。导线测试部分和电极测试部分分别具有与导电线和第一电极基本上相同的宽度。测试构件还包括半导体层测试部分。显示基板有助于有效的制造，缩短了处理时间和成本。

23. 发明授权

US07745823B2 Thin film panel and method of manufacturing the same 有权
标题翻译：薄膜面板及其制造方法
公开(公告)号：US07745823B2
公开(公告)日：2010-06-29
申请号：US11479233
申请日：2006-06-30
申请人： Dong-Hyeon Ki
发明人： Dong-Hyeon Ki
IPC分类号： H01L31/00
CPC分类号： G09G3/006 , G02F1/136286 , G02F2001/136254 , G02F2001/136272 , H01L27/3276
摘要： A thin film panel is provided, which includes a first signal line and a second signal line crossing the first signal line and formed on a different layer from the first signal line. The second signal line includes an expansion having an enlarged area and at least one cutout, and is disposed adjacent to a crossing region where the second signal line crosses the first signal line.
摘要翻译：提供薄膜面板，其包括与第一信号线交叉并形成在与第一信号线不同的层上的第一信号线和第二信号线。第二信号线包括具有放大区域的扩展和至少一个切口，并且与第二信号线穿过第一信号线的交叉区域相邻设置。

24. 发明申请

US20070034522A1 Display substrate for easy detection of pattern misalignment 有权
标题翻译：显示基板，便于检测图案不对准
公开(公告)号：US20070034522A1
公开(公告)日：2007-02-15
申请号：US11502915
申请日：2006-08-10
申请人： Jung-Joon Park , Min-Wook Park , Dong-Hyeon Ki
发明人： Jung-Joon Park , Min-Wook Park , Dong-Hyeon Ki
IPC分类号： C25B1/34
CPC分类号： G02F1/136259 , G02F2001/136254
摘要： A display substrate includes a base substrate, a conductive line on the base substrate, a switching element and a testing member. The switching element includes a first electrode formed on the semiconductor layer pattern and electrically connected to the conductive line, and a second electrode spaced apart from the first electrode and semiconductor layer pattern. The testing member includes a conductive line testing portion that is formed from the same layer as the conductive line and an electrode testing portion that is formed from the same layer as the first electrode. The conductive line testing portion and the electrode testing portion have substantially the same width as the conductive line and the first electrode, respectively. The testing member also includes a semiconductor layer testing portion. The display substrate lends itself to efficient manufacturing with reduced process time and cost.
摘要翻译：显示基板包括基底基板，基底基板上的导线，开关元件和测试部件。开关元件包括形成在半导体层图案上并电连接到导电线的第一电极和与第一电极和半导体层图案间隔开的第二电极。测试构件包括由与导电线相同的层形成的导线测试部分和由与第一电极相同的层形成的电极测试部分。导线测试部分和电极测试部分分别具有与导电线和第一电极基本上相同的宽度。测试构件还包括半导体层测试部分。显示基板有助于有效的制造，缩短了处理时间和成本。

25. 发明授权

US07130003B2 Thin film transistor array substrate for a liquid crystal display and the method for fabricating the same 有权
公开(公告)号：US07130003B2
公开(公告)日：2006-10-31
申请号：US11126305
申请日：2005-05-11
申请人： Woon-Yong Park , Hyeon-Hwan Kim , Dong-Hyeon Ki
发明人： Woon-Yong Park , Hyeon-Hwan Kim , Dong-Hyeon Ki
IPC分类号： G02F1/1333 , G02F1/1343 , H01L21/00
CPC分类号： H01L29/66765 , G02F1/134363 , G02F1/13458 , G02F1/1368 , G02F2001/136231 , H01L27/12 , H01L29/78669
摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.

26. 发明申请

US20060157705A1 Thin film transistor array panel 审中-公开
标题翻译：薄膜晶体管阵列面板
公开(公告)号：US20060157705A1
公开(公告)日：2006-07-20
申请号：US11325894
申请日：2006-01-04
申请人： Dong-Hyeon Ki
发明人： Dong-Hyeon Ki
IPC分类号： H01L29/04 , G02F1/136
CPC分类号： G02F1/136227 , G02F2001/136222 , H01L27/124 , H01L27/1255
摘要： A thin film transistor array panel is provided, comprising: a gate line on an insulating substrate; a storage electrode line on the insulating substrate; a gate insulating layer over the gate line and the storage electrode line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode on the semiconductor layer and separated from each other; a lower passivation layer formed on the semiconductor layer and having a first contact hole exposing the drain electrode; a color filter on the lower passivation layer; an upper passivation layer on the color filter and having a second contact hole exposing the drain electrode; and a pixel electrode connected to the drain electrode through the first and second contact holes; wherein the storage electrode line has a light blocking member parallel to the data line.
摘要翻译：提供一种薄膜晶体管阵列面板，包括：绝缘基板上的栅极线; 绝缘基板上的存储电极线; 栅极线上的栅极绝缘层和存储电极线; 栅极绝缘层上的半导体层; 半导体层上的数据线和漏电极，彼此分离; 形成在所述半导体层上并具有暴露所述漏电极的第一接触孔的下钝化层; 下钝化层上的滤色器; 滤色器上的上钝化层，并具有暴露漏电极的第二接触孔; 以及通过所述第一和第二接触孔与所述漏电极连接的像素电极; 其中所述存储电极线具有与所述数据线平行的遮光部件。

27. 发明授权

US06678018B2 Thin film transistor array substrate for a liquid crystal display and the method for fabricating the same 有权
标题翻译：液晶显示器用薄膜晶体管阵列基板及其制造方法
公开(公告)号：US06678018B2
公开(公告)日：2004-01-13
申请号：US09779705
申请日：2001-02-09
申请人： Woon-Yong Park , Hyeon-Hwan Kim , Dong-Hyeon Ki
发明人： Woon-Yong Park , Hyeon-Hwan Kim , Dong-Hyeon Ki
IPC分类号： G02F1136
CPC分类号： H01L29/66765 , G02F1/134363 , G02F1/13458 , G02F1/1368 , G02F2001/136231 , H01L27/12 , H01L29/78669
摘要： A method for fabricating a thin film array substrate for a liquid crystal display includes steps of forming a gate line assembly and a common electrode line assembly on a first substrate. The gate line assembly includes a plurality of gate lines and gate pads, and the common electrode line assembly includes common signal lines and common electrodes. Thereafter, a gate insulating layer is formed on the first substrate, and a semiconductor pattern and an ohmic contact pattern are formed on the gate insulating layer. A data line assembly and pixel electrodes are then formed on the first substrate. The data line assembly includes a plurality of data lines, data pads, and source and drain electrodes. The pixel electrodes are connected to the drain electrodes while proceeding parallel to the common electrodes. A passivation layer is formed on the substrate. The passivation layer and the gate insulating layer are etched such that the gate pads and the data pads are exposed to the outside. At this time, the etching is performed after an assembly process where a second substrate is arranged to face the first substrate and assembled together and the passivation layer and the gate insulating layer are exposed outside of the second substrate.
摘要翻译：制造液晶显示器用薄膜阵列基板的方法包括在第一基板上形成栅线组合体和公共电极线组合体的工序。栅极线组件包括多个栅极线和栅极焊盘，并且公共电极线组件包括公共信号线和公共电极。此后，在第一基板上形成栅极绝缘层，并且在栅极绝缘层上形成半导体图案和欧姆接触图案。然后在第一基板上形成数据线组件和像素电极。数据线组件包括多条数据线，数据焊盘以及源极和漏极。像素电极在平行于公共电极的同时连接到漏电极。在衬底上形成钝化层。蚀刻钝化层和栅极绝缘层，使得栅极焊盘和数据焊盘暴露于外部。此时，在将第二基板布置成面对第一基板并组装在一起并且钝化层和栅极绝缘层暴露在第二基板外部的组装工艺之后进行蚀刻。

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