专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07158521B2 Synchronization system and synchronization method of multisystem control apparatus 失效
标题翻译：多系统控制装置的同步系统和同步方法
公开(公告)号：US07158521B2
公开(公告)日：2007-01-02
申请号：US10098509
申请日：2002-03-18
申请人： Yuichiro Morita , Kotaro Shimamura , Yoshitaka Takahashi , Takashi Hotta , Kazuhiro Imaie , Shigeta Ueda , Akira Bando , Mitsuyasu Kido , Takeshi Takehara
发明人： Yuichiro Morita , Kotaro Shimamura , Yoshitaka Takahashi , Takashi Hotta , Kazuhiro Imaie , Shigeta Ueda , Akira Bando , Mitsuyasu Kido , Takeshi Takehara
IPC分类号： H04L12/22 , H04L12/56
CPC分类号： G06F11/184 , G06F1/12 , G06F11/0736 , G06F11/0772 , G06F11/0793 , G06F11/165 , G06F11/1675
摘要： In a synchronization system adopted in a synchronous-multisystem control apparatus comprising a plurality of systems operating synchronously with each other at a fixed control period, the synchronous-multisystem control apparatus can be operated in a single-system mode in the event of failures occurring simultaneously in some of the systems.The synchronous-multisystem control apparatus employs a plurality of control circuits each provided for one of the systems. Any particular one of the control circuits comprises: a period-signal generating circuit for generating a period signal indicating a start point of a control period; a synchronization-reference selecting circuit for outputting a synchronization-reference signal by referring to period signals generated by the systems; and a control-period correcting circuit for correcting a control period of the particular system by forming a judgment on a synchronization shift of the period signal generated by the particular system from the synchronization-reference signal and keeping the control period as it is in case the synchronization-reference signal is not generated.
摘要翻译：在同步多系统控制装置中采用的同步系统中，包括在固定的控制周期内彼此同步操作的多个系统，同步多系统控制装置可以在同时发生故障的情况下以单系统模式操作在一些系统中。同步多系统控制装置采用多个控制电路，每个控制电路为系统之一提供。任何一个控制电路包括：周期信号产生电路，用于产生指示控制周期的起始点的周期信号; 同步参考选择电路，用于通过参考系统产生的周期信号来输出同步参考信号; 以及控制周期校正电路，用于通过根据同步参考信号形成对由特定系统产生的周期信号的同步偏移的判断来校正特定系统的控制周期，并且保持控制周期为原样，不产生同步参考信号。

22. 发明授权

US5684729A Floating-point addition/substraction processing apparatus and method thereof 失效
标题翻译：浮点加法/减法处理装置及其方法
公开(公告)号：US5684729A
公开(公告)日：1997-11-04
申请号：US530471
申请日：1995-09-19
申请人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
发明人： Hiromichi Yamada , Fumio Murabayashi , Tatsumi Yamauchi , Takashi Hotta , Hideo Sawamoto , Takahiro Nishiyama , Yoshikazu Kiyoshige , Noriyasu Ido
IPC分类号： G06F7/50 , G06F7/74
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49947 , G06F7/49994
摘要： To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.
摘要翻译：为了提供能够缩短计算时间的浮点加法/减法处理装置及其方法，浮点计算处理装置包括：近似移位预测单元，用于通过使用输入浮点运算处理装置预测用于归一化的移位量，点数据在1比特的误差内进行加法/减法处理;移位误差检测单元，用于检测预测偏移量和正确移位量之间的差;以及位移移位器，用于校正结果，移位量乘以检测到的两个移动量的差异，其中在执行归一化移位处理之前并行处理舍入确定和移位量计算。

23. 发明授权

US07424598B2 Data processor 失效
标题翻译：数据处理器
公开(公告)号：US07424598B2
公开(公告)日：2008-09-09
申请号：US09853769
申请日：2001-05-14
申请人： Takashi Hotta , Shigeya Tanaka , Hideo Maejima
发明人： Takashi Hotta , Shigeya Tanaka , Hideo Maejima
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/3889 , G06F9/3802 , G06F9/3824 , G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： The data processor for executing, instructions realized by wired logic, by a pipeline system, includes a plurality of instruction registers, and arithmetic operation units of the same number. A plurality of instructions read in the instruction registers in one machine cycle at a time are processed in parallel by the plurality of arithmetic operation units.
摘要翻译：用于由管线系统执行由有线逻辑实现的指令的数据处理器包括多个指令寄存器和相同数量的算术运算单元。一次在一个机器周期中在指令寄存器中读取的多个指令由多个算术运算单元并行处理。

24. 发明授权

US5968160A Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory 失效
标题翻译：根据程序的并行性通过使用高速缓冲存储器来处理多种模式的数据的方法和装置
公开(公告)号：US5968160A
公开(公告)日：1999-10-19
申请号：US923632
申请日：1997-09-04
申请人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
发明人： Masahiko Saito , Kenichi Kurosawa , Yoshiki Kobayashi , Tadaaki Bandoh , Masahiro Iwamura , Takashi Hotta , Yasuhiro Nakatsuka , Shigeya Tanaka , Takeshi Takemoto
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F12/08 , G06F15/173 , G06F15/80 , G06F15/16
CPC分类号： G06F9/3891 , G06F12/084 , G06F15/17381 , G06F15/8015 , G06F9/30087 , G06F9/3009 , G06F9/30181 , G06F9/3802 , G06F9/3814 , G06F9/3822 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3885
摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.
摘要翻译：具有应对程序的并行性的灵活性的数据处理系统包括用于执行指令的多个处理器元件，由多个处理器元件共享的主存储器和用于使多个处理器元件能够操作的多个并行操作控制设备同步。分别对应于多个处理器元件提供多个并行操作控制设备。数据处理系统还包括多处理器操作控制设备，用于使多个处理器元件能够独立地操作，以及用于保持指示并行操作模式或多处理器模式中的哪一个被激活的值的标志。共享高速缓冲存储器以空白指令实现并由高速缓存控制器控制，从而消除了存储在高速缓冲存储器中的数据的不一致性。

25. 发明授权

US5894582A Method of controlling parallel processing at an instruction level and processor for realizing the method 失效
标题翻译：在指令级别控制并行处理的方法和用于实现该方法的处理器
公开(公告)号：US5894582A
公开(公告)日：1999-04-13
申请号：US596628
申请日：1996-02-05
申请人： Shoji Yoshida , Takashi Hotta , Shigeya Tanaka
发明人： Shoji Yoshida , Takashi Hotta , Shigeya Tanaka
IPC分类号： G06F9/38 , G06F9/28
CPC分类号： G06F9/3853
摘要： Apparatus for realizing instruction level parallel processing includes an instruction buffer for storing instructions fetched from a memory until the instructions are sent from the instruction buffer, an instruction register unit for storing and issuing the sent instructions to a plurality of execution units in the order of instruction, and a judgement part for judging whether it is possible to execute a set of unissued instructions to be next issued, in parallel, as stored in the instruction buffer and/or the instruction register unit and for controlling parallel processing of the set of instructions, based on the result of a judgement on the possibility of parallel processing.
摘要翻译：用于实现指令级并行处理的装置包括：指令缓冲器，用于存储从指令缓冲器发送指令之前从存储器取出的指令;指令寄存器单元，用于以指令顺序存储并发布发送指令给多个执行单元; 以及用于判断是否可以并行地执行存储在指令缓冲器和/或指令寄存器单元中并用于控制该组指令的并行处理的一组未发布指令的判断部分，基于对并行处理可能性的判断结果。

26. 发明授权

US5713012A Microprocessor 失效
标题翻译：微处理器
公开(公告)号：US5713012A
公开(公告)日：1998-01-27
申请号：US717143
申请日：1996-09-20
申请人： Shigeya Tanaka , Takashi Hotta , Shoji Yoshida , Kenji Jin , Koji Saito
发明人： Shigeya Tanaka , Takashi Hotta , Shoji Yoshida , Kenji Jin , Koji Saito
IPC分类号： G06F9/38 , G06F9/40
CPC分类号： G06F9/3836 , G06F9/3861 , G06F9/3885
摘要： A microprocessor has N processing units, a detector for detecting a branch instruction (k-th instruction) which comes first in the instruction sequence of N instructions, function logic for effecting control such that the first to the k-th instructions are executed with the (N-k+1)-th through the N-th processing units. However, when parallel processing is possible, the function logic operates such that the first through the N-th instructions are executed in sequential order by the first through the N-th processing units. On the other hand, wherein a branch instruction (k-th instruction) is included in the N sequential instructions, the function logic operates such that the first through the k-th instructions are parallelly executed by the (N-p+1)-th through the N-th processing units.
摘要翻译：微处理器具有N个处理单元，用于检测在N个指令的指令序列中首先出现的分支指令（第k指令）的检测器，用于进行控制的功能逻辑，使得第一到第k指令被执行（N-k + 1）到第N个处理单元。然而，当并行处理是可能的时候，功能逻辑操作使得第一到第N指令由第一到第N个处理单元按顺序执行。另一方面，其中在N个顺序指令中包括分支指令（第k指令），功能逻辑运算，使得第一至第k指令由（N-p + 1） - 通过第N个处理单元。

27. 发明授权

US5506982A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
公开(公告)号：US5506982A
公开(公告)日：1996-04-09
申请号：US278245
申请日：1994-07-21
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/06
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

28. 发明授权

US06675311B2 Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
标题翻译：数据处理系统从输入时钟产生时钟信号，锁相到输入时钟并用于时钟逻辑器件
公开(公告)号：US06675311B2
公开(公告)日：2004-01-06
申请号：US10002444
申请日：2001-12-06
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F104
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生至少一个第二时钟信号K1与原始时钟信号K锁相并具有预定的占空比，以及由第二时钟信号K1控制其操作定时的逻辑器件。至少一对逻辑设备由时钟信号K1同步控制。

29. 发明授权

US07111187B2 Information processor and information processing system utilizing interface for synchronizing clock signal 失效
标题翻译：信息处理器和信息处理系统利用界面来同步时钟信号
公开(公告)号：US07111187B2
公开(公告)日：2006-09-19
申请号：US10701447
申请日：2003-11-06
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/04
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.
摘要翻译：一种具有原始时钟振荡器的信息处理系统，用于传送被定义为第一时钟信号的至少一个原始时钟信号K和提供有原始时钟信号K的多个信息处理单元，其中每个信息处理单元包括时钟发生装置，用于产生与原始时钟信号K锁相并且具有预定占空比的至少一个第二时钟信号K 1 1和其操作时序被第二时钟信号K _{1 <1>，并且由至少一对逻辑器件之间提供的接口的操作时序由时钟信号K 1 1同步地控制。}

30. 发明授权

US06467004B1 Pipelined semiconductor devices suitable for ultra large scale integration 失效
标题翻译：适用于超大规模集成的流水线半导体器件
公开(公告)号：US06467004B1
公开(公告)日：2002-10-15
申请号：US09477448
申请日：2000-01-04
申请人： Masahiro Iwamura , Shigeya Tanaka , Takashi Hotta , Tatsumi Yamauchi , Kazutaka Mori
发明人： Masahiro Iwamura , Shigeya Tanaka , Takashi Hotta , Tatsumi Yamauchi , Kazutaka Mori
IPC分类号： G06F938
CPC分类号： G06F9/3875 , G06F9/3869
摘要： A high speed, high performance pipelined semiconductor device is provided, such as a pipelined data processing device and memory device. In the pipeline operation, a functional circuit unit and a transmission unit are separately controlled at each pipeline stage cycle. A transmission unit between two functional circuit units is divided into N transmission units while considering a cycle time, and each divided transmission unit is assigned one pipeline stage cycle.
摘要翻译：提供了一种高速，高性能流水线半导体器件，例如流水线数据处理设备和存储器件。在流水线操作中，功能电路单元和传输单元在每个流水线级周期被单独控制。两个功能电路单元之间的传输单元在考虑周期时间的同时被分成N个传输单元，并且每个划分的传输单元被分配一个流水线级周期。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式