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21. 发明授权

US5963502A Clock-synchronous type semiconductor memory device capable of outputting read clock signal at correct timing 失效
标题翻译：时钟同步型半导体存储器件能够以正确的时序输出读时钟信号
公开(公告)号：US5963502A
公开(公告)日：1999-10-05
申请号：US112439
申请日：1998-07-09
申请人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
发明人： Naoya Watanabe , Yoshikazu Morooka , Tsutomu Yoshimura , Yasunobu Nakase
IPC分类号： G11C11/413 , G11C7/10 , G11C7/22 , G11C11/407 , G11C11/409 , H03L7/06 , G11C7/00
CPC分类号： G11C7/22 , G11C7/1072
摘要： A voltage controlled delay circuit having the same structure, except for a loop, as a voltage controlled oscillator included in a PLL circuit which in turn generates an internal clock signal from an external clock signal is controlled by a control voltage from the PLL circuit, and the delay output of the voltage controlled delay circuit is selected by a selection circuit in accordance with the output signal of a vernier-adjusting counter in order to generate a read clock signal. Therefore, a vernier for optimizing data input timing in a controller can be realized which always has a constant delay amount regardless of a change in operating environment.
摘要翻译：作为包括在PLL电路中的压控振荡器，具有与循环不同的结构的电压控制延迟电路，该PLL电路又由外部时钟信号产生内部时钟信号，由PLL电路的控制电压控制，电压控制延迟电路的延迟输出由选择电路根据游标调节计数器的输出信号选择，以产生读时钟信号。因此，可以实现用于优化控制器中的数据输入定时的游标，其总是具有恒定的延迟量，而与操作环境的变化无关。

22. 发明授权

US5699303A Semiconductor memory device having controllable supplying capability of internal voltage 失效
标题翻译：具有可控的内部电压供应能力的半导体存储器件
公开(公告)号：US5699303A
公开(公告)日：1997-12-16
申请号：US645347
申请日：1996-05-13
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.
摘要翻译：当外部+ E，ovs RAS + EE和外部+ E，ovs CAS + EE输入到RAS缓冲区，CAS缓冲区，内部+ E，ovs RAS + EE和内部+ E，ovs CAS + EE 生成。内部+ E，ovs RAS + EE输入到时钟发生电路和CBR模式确定电路，内部+ E，ovs CAS + EE输入到CBR模式确定电路。时钟发生电路在内部+ E，RAS + EE输入时向第一和第二WL泵输出泵时钟，第一WL泵为Vpp电源供电。如果+ E，则在+ E之前输入ovs CAS + EE，在刷新操作期间输入ovs RAS + EE，CBR模式确定电路将CBR模式信号输入到与第一WL泵一起向Vpp电源提供电荷的第二WL泵当泵时钟和CBR模式信号被输入时。

23. 发明授权

US5481496A Semiconductor memory device and method of data transfer therefor 失效
标题翻译：半导体存储器件及其数据传输方法
公开(公告)号：US5481496A
公开(公告)日：1996-01-02
申请号：US236004
申请日：1994-05-02
申请人： Toshifumi Kobayashi , Yoshikazu Morooka , Michihiro Yamada , Takeshi Hamamoto
发明人： Toshifumi Kobayashi , Yoshikazu Morooka , Michihiro Yamada , Takeshi Hamamoto
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C7/00 , G11C8/00
CPC分类号： G11C7/065 , G11C7/1006 , G11C7/12
摘要： Sense amplifiers provided for each of the bit line pairs are divided into groups to be independently driven, whereby the influence of sense amplifiers of different groups can be prevented, and therefore the destruction of data of the non-selected memory cells during data transfer can be prevented. In transferring data from the data register to the memory cell array, the sense amplifier is not activated until the stored information of the memory cells selected by the word line is fully read to the corresponding bit lines, whereby the destruction of data stored in the non-selected memory cells can be prevented.
摘要翻译：为每个位线对提供的感测放大器被分成要被独立驱动的组，由此可以防止不同组的读出放大器的影响，因此数据传送期间未选择的存储器单元的数据的破坏可以是防止了在将数据从数据寄存器传送到存储单元阵列时，读出放大器不会被激活，直到由字线选择的存储单元的存储信息被完全读出到相应的位线为止，可以防止选择的存储单元。

24. 发明授权

US06658639B2 Semiconductor integrated circuit provided with determination circuit 失效
标题翻译：半导体集成电路配有确定电路
公开(公告)号：US06658639B2
公开(公告)日：2003-12-02
申请号：US09860612
申请日：2001-05-21
申请人： Yoshikazu Morooka
发明人： Yoshikazu Morooka
IPC分类号： G06F1750
CPC分类号： G01R31/31724 , G01R31/31707
摘要： A semiconductor integrated circuit capable of determining a configuration of a plurality of elements included in a functional block is provided. The semiconductor integrated circuit includes a memory functional block with a variable storage capacity, a functional block, and a terminal group for testing. A plurality of sub blocks are formed in the memory functional block when a chip is formed. Each of the plurality of sub blocks includes a determination circuit having substantially the same structure and function. A signal is input to the determination circuit from the terminal group, and a signal output through the determination circuit is observed at the terminal group. This enables determination of the configuration (the number, positional relationship, or the like) of the sub blocks.
摘要翻译：提供一种能够确定包括在功能块中的多个元素的配置的半导体集成电路。半导体集成电路包括具有可变存储容量的存储功能块，功能块和用于测试的终端组。当形成芯片时，在存储功能块中形成多个子块。多个子块中的每一个包括具有基本上相同结构和功能的确定电路。信号从终端组输入到确定电路，并且在端子组处观察到通过确定电路输出的信号。这使得能够确定子块的配置（数量，位置关系等）。

25. 发明授权

US06442644B1 Memory system having synchronous-link DRAM (SLDRAM) devices and controller 失效
标题翻译：具有同步链路DRAM（SLDRAM）器件和控制器的存储器系统
公开(公告)号：US06442644B1
公开(公告)日：2002-08-27
申请号：US09132158
申请日：1998-08-10
申请人： David B. Gustavson , David V. James , Hans A. Wiggers , Peter B. Gillingham , Cormac M. O'Connell , Bruce Millar , Jean Crepeau , Kevin J. Ryan , Terry R. Lee , Brent Keeth , Troy A. Manning , Donald N. North , Desi Rhoden , Henry Stracovsky , Yoshikazu Morooka
发明人： David B. Gustavson , David V. James , Hans A. Wiggers , Peter B. Gillingham , Cormac M. O'Connell , Bruce Millar , Jean Crepeau , Kevin J. Ryan , Terry R. Lee , Brent Keeth , Troy A. Manning , Donald N. North , Desi Rhoden , Henry Stracovsky , Yoshikazu Morooka
IPC分类号： G06F1200
CPC分类号： G11C7/1066 , G06F13/409 , G06F13/4243 , G11C7/10 , G11C7/1012 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1087 , G11C7/109 , G11C7/22 , G11C2207/2254 , H05K1/0219 , H05K1/0246 , H05K2201/0715 , H05K2201/09236 , H05K2201/09254 , H05K2201/09309 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689 , Y02D10/14 , Y02D10/151
摘要： A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.
摘要翻译： SLDRAM系统配备有多个在线可校准存储器模块和用于向存储器模块发出单播和多播命令分组的存储器控制器。命令分组通过单向命令链路发送，该单向命令链路包括一对互补的命令时钟线，命令FLAG线和多个未实现的命令位线。每个命令时钟线，命令位线和FLAG线都是SLIO传输线。响应于一个或多个双向数据链路上的命令分组执行数据传送操作，每个双向数据链路包括两对互补的数据时钟线对，以及多个未实现的数据位线。每个数据时钟线和数据位线都是SLIO传输线。每个SLIO传输线都是单端端接的，最好采用短截线电阻。

26. 发明授权

US06392897B1 Circuit module 失效
标题翻译：电路模块
公开(公告)号：US06392897B1
公开(公告)日：2002-05-21
申请号：US09131688
申请日：1998-08-10
申请人： Yasunobu Nakase , Tsutomu Yoshimura , Yoshikazu Morooka , Naoya Watanabe
发明人： Yasunobu Nakase , Tsutomu Yoshimura , Yoshikazu Morooka , Naoya Watanabe
IPC分类号： H01R1216
CPC分类号： H05K1/14 , H05K1/117 , H05K3/403 , H05K2201/09481 , H05K2201/10159 , H05K2201/10689 , H05K2203/1572
摘要： A circuit module includes a connector terminal (4A) provided on a front surface of a printed wiring board (2) and connected to a data pin (DQt) of a memory IC (3) through an interconnect line (5a). A conductive connector terminal (4c) corresponds to the connector terminal (4a) and is provided on a back surface of the printed wiring board (2). A through hole (16) extends between part of the front surface of the printed wiring board (2) where the connector terminal (4a) is formed and part of the back surface thereof where the conductive connector terminal (4c) is formed. A conductor fills the through hole (16), thereby suppressing skews resulting from a difference in interconnect line length on the circuit module and decreasing a stub capacitance to achieve the reduction in power consumption.
摘要翻译：电路模块包括设置在印刷电路板（2）的前表面并通过互连线（5a）连接到存储器IC（3）的数据引脚（DQt）的连接器端子（4A）。导电连接器端子（4c）对应于连接器端子（4a）并且设置在印刷电路板（2）的背面上。在形成有连接器端子（4a）的印刷电路板（2）的前表面的一部分和形成导电连接器端子（4c）的背面的一部分之间延伸有一个通孔（16）。导体填充通孔（16），从而抑制由电路模块上的互连线长度的差异引起的偏移，并且减小短截线电容以实现功耗的降低。

27. 发明授权

US5994934A Delay locked loop circuit 失效
标题翻译：延时锁定回路电路
公开(公告)号：US5994934A
公开(公告)日：1999-11-30
申请号：US111875
申请日：1998-07-08
申请人： Tsutomu Yoshimura , Yasunobu Nakase , Yoshikazu Morooka , Naoya Watanabe , Harufusa Kondoh , Hiromi Notani
发明人： Tsutomu Yoshimura , Yasunobu Nakase , Yoshikazu Morooka , Naoya Watanabe , Harufusa Kondoh , Hiromi Notani
IPC分类号： G06F1/10 , G11C11/4076 , H03K5/00 , H03K5/13 , H03K5/131 , H03L7/00 , H03L7/081 , H03L7/089 , H03L7/095 , H03L7/06
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/095
摘要： Provided is a DLL circuit that can execute a precise delay synchronization operation without increasing the variable delay time range of a delay line. The DLL circuit comprises a phase comparator (3), a charge pump (6), an LPF (8) and a delay line (9), and operates to match phases of an input signal (CLKIN) and a feedback signal (FBCLK). The phase comparator (3) always outputs a phase comparison result that causes a delay time of the delay line (9) to increase, at the time of initial operation after a reset operation. The LPF (8) outputs a delay adjusting signal (S8) indicating that a delay time due to the delay line (9) becomes the minimum, in executing a reset.
摘要翻译：提供了可以在不增加延迟线的可变延迟时间范围的情况下执行精确的延迟同步操作的DLL电路。 DLL电路包括相位比较器（3），电荷泵（6），LPF（8）和延迟线（9），并且操作以匹配输入信号（CLKIN）和反馈信号（FBCLK）的相位，。相位比较器（3）总是输出在复位操作之后的初始操作时延迟线（9）的延迟时间增加的相位比较结果。在执行复位时，LPF（8）输出指示由于延迟线（9）引起的延迟时间变为最小的延迟调整信号（S8）。

28. 发明授权

US5926837A Memory system capable of reducing timing skew between clock signal and data 失效
标题翻译：存储系统能够减少时钟信号与数据之间的时序偏差
公开(公告)号：US5926837A
公开(公告)日：1999-07-20
申请号：US815989
申请日：1997-03-10
申请人： Naoya Watanabe , Yoshikazu Morooka
发明人： Naoya Watanabe , Yoshikazu Morooka
IPC分类号： G06F12/00 , G06F13/16 , G11C11/401
CPC分类号： G06F13/1689
摘要： A memory system includes a data bus which is folded, a clock signal line extending in parallel with the data bus for transferring a clock signal, memories connected to the data bus and the clock signal line, and memories controller for controlling the memories, wherein the memory controller generates a clock signal to supply it to one end of the clock signal line, and is responsive to a clock signal input from another end of the clock signal line to receive data output from the memory from one end of the data bus.
摘要翻译：存储器系统包括被折叠的数据总线，与用于传送时钟信号的数据总线并行延伸的时钟信号线，连接到数据总线和时钟信号线的存储器，以及用于控制存储器的存储器控制器，其中，存储器控制器产生时钟信号以将其提供给时钟信号线的一端，并且响应于从时钟信号线的另一端输入的时钟信号，以从数据总线的一端接收从存储器输出的数据。

29. 发明授权

US5841705A Semiconductor memory device having controllable supplying capability of internal voltage 失效
公开(公告)号：US5841705A
公开(公告)日：1998-11-24
申请号：US924501
申请日：1997-09-05
申请人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
发明人： Takeshi Hamamoto , Kiyohiro Furutani , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C5/14 , G11C11/403 , G11C11/406 , G11C11/4074 , G11C11/408 , G11C11/409 , G11C13/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4074 , G11C5/146
摘要： When an external RAS and external CAS are input to a RAS buffer and a CAS buffer, an internal RAS and an internal CAS are generated. The internal RAS is input to a clock generating circuit and a CBR mode determination circuit and the internal CAS is input to the CBR mode determination circuit. The clock generating circuit outputs a pump clock to first and second WL pumps upon input of internal RAS, and the first WL pump supplies charge to a Vpp power supply. If CAS is input prior to RAS during refresh operation, CBR mode determination circuit inputs a CBR mode signal to the second WL pump which supplies charge to Vpp power supply together with the first WL pump when the pump clock and the CBR mode signal is input thereto.

30. 发明授权

US5200925A Serial access semiconductor memory device and operating method therefor 失效
标题翻译：串行存取半导体存储器件及其操作方法
公开(公告)号：US5200925A
公开(公告)日：1993-04-06
申请号：US728323
申请日：1991-07-08
申请人： Yoshikazu Morooka
发明人： Yoshikazu Morooka
IPC分类号： G11C7/10
CPC分类号： G11C7/103
摘要： A serially accessible memory device includes a plurality of memory cell array blocks, a plurality of input buffers each separately provided for each cell array block for receiving different data in a data stream, a plurality of output buffers each separately provided for each memory cell array block, and a plurality of registers each separately provided for each memory cell array block for effectuating data transfer collectively to and from corresponding memory cell array blocks at the same time. All of the registers shift data received from corresponding input buffer to latch the data therein in response to a single clock signal in a data writing operation and also shift latched data received from corresponding array block to provide the data to corresponding output buffer in response to another single clock signal in data reading operation. Both the shifting clock signals are derived from an external clock defining the device operation rate.
摘要翻译：一种可串行存取的存储器件包括多个存储单元阵列块，多个输入缓冲器，分别为每个单元阵列块提供用于接收数据流中的不同数据;多个输出缓冲器，每个分别为每个存储单元阵列块提供，以及分别为每个存储单元阵列块提供的多个寄存器，用于同时实现与相应的存储单元阵列块的数据传输。所有这些寄存器移位从相应的输入缓冲器接收到的数据，以在数据写入操作中响应于单个时钟信号来锁存其中的数据，并且还移位从对应的阵列块接收的锁存数据，以响应于另一个向相应的输出缓冲器提供数据单时钟信号在数据读取操作。两个移位时钟信号都是从定义设备运行速率的外部时钟导出的。

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