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21. 发明授权

US4780850A CMOS dynamic random access memory 失效
标题翻译： CMOS动态随机存取存储器
公开(公告)号：US4780850A
公开(公告)日：1988-10-25
申请号：US116285
申请日：1987-11-02
申请人： Hiroshi Miyamoto , Shigeru Mori , Michihiro Yamada , Tadato Yamagata
发明人： Hiroshi Miyamoto , Shigeru Mori , Michihiro Yamada , Tadato Yamagata
IPC分类号： G11C11/4091 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4094
摘要： A dynamic random access memory comprises N channel sense amplifiers, P channel sense amplifiers and an equalizing MOSFET each provided for each of bit line pairs. The N channel sense amplifiers and the P channel sense amplifiers are operated by sense amplifier driving signals. In each of the N channel sense amplifiers, an MOSFET is connected between one of bit lines and an interconnection for transmitting a sense amplifier driving signal. In addition, a precharge potential generating circuit for generating a potential of (1/2)V.sub.CC is connected to the interconnection for transmitting the sense amplifier driving signal through a MOSFET. The bit line pairs are equalized by the equalizing MOSFET. Then, in each of the N channel sense amplifiers, the above described interconnection and one of the bit lines are connected to each other, and the above described interconnection and the precharge potential generating circuit are connected to each other. Therefore, the potentials on the bit line pairs and the above described interconnection are held at (1/2)V.sub.CC.
摘要翻译：动态随机存取存储器包括N个通道读出放大器，P沟道读出放大器和均匀化的MOSFET，每个均为每个位线对提供。 N沟道读出放大器和P沟道读出放大器由读出放大器驱动信号操作。在每个N沟道读出放大器中，MOSFET连接在位线之一和用于传输读出放大器驱动信号的互连之间。此外，用于产生（1/2）VCC的电位的预充电电位发生电路连接到用于通过MOSFET传输读出放大器驱动信号的互连。位线对由均衡MOSFET均衡。然后，在N个通道读出放大器的每一个中，上述互连和一个位线彼此连接，并且上述互连和预充电电势产生电路彼此连接。因此，位线对上的电位和上述互连保持在（1/2）VCC。

22. 发明授权

US4739500A Dynamic ram having folded bit line structure 失效
标题翻译：具有折叠位线结构的动态柱塞
公开(公告)号：US4739500A
公开(公告)日：1988-04-19
申请号：US14837
申请日：1987-02-13
申请人： Hiroshi Miyamoto , Michihiro Yamada
发明人： Hiroshi Miyamoto , Michihiro Yamada
IPC分类号： G11C11/401 , G11C11/4091 , G11C11/4097 , G11C7/02 , G11C7/00
CPC分类号： G11C11/4091 , G11C11/4097
摘要： A dynamic RAM comprises a sense amplifier and a restore circuit for each pair of divided bit lines. Sense operation can be performed in a fast and stable manner and the gate voltage of a transfer gate transistor need not be boosted over the power supply potential, so that the access time of the dynamic RAM can be reduced, operation margin thereof is increased, and reliability is improved.
摘要翻译：动态RAM包括用于每对分割位线的读出放大器和恢复电路。可以以快速且稳定的方式执行感测操作，并且传递栅极晶体管的栅极电压不需要在电源电位上升压，使得动态RAM的存取时间可以减小，其操作余量增加，并且可靠性提高。

23. 发明授权

US4724341A CMOS decoder circuit resistant to latch-up 失效
标题翻译： CMOS解码电路可以防闩锁
公开(公告)号：US4724341A
公开(公告)日：1988-02-09
申请号：US941214
申请日：1986-12-12
申请人： Michihiro Yamada , Hiroshi Miyamoto
发明人： Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： H03M7/00 , H03K17/693 , H03K17/56 , G06F7/38 , H03K19/094
CPC分类号： H03K17/693
摘要： A decoder part is formed by a main decoder part C and a plurality of subdecoder parts D.sub.0 to D.sub.3 connected with the main decoder part C, and a plurality of such decoder parts are provided. In such structure, the main decoder part specifies one of a plurality of decoder parts and a CMOS circuit (PMOS transistor T.sub.0 and NMOS transistors T.sub.0 ', . . . , PMOS transistor and NMOS transistor T.sub.3 ') specifies one of the subdecoder parts and PMOS transistors (T.sub.00 to T.sub.03, . . . , T.sub.30 to T.sub.33) select finally decoded output.
摘要翻译：解码器部分由主解码器部分C和与主解码器部分C连接的多个子解码器部分D0至D3形成，并且提供多个这样的解码器部分。在这种结构中，主解码器部分指定多个解码器部分中的一个，并且CMOS电路（PMOS晶体管T0和NMOS晶体管T0'，...，PMOS晶体管和NMOS晶体管T3'）指定子编码器部分和PMOS 晶体管（T00至T03，...，T30至T33）选择最终解码输出。

24. 发明授权

US4641281A Dynamic random access memory with hidden refresh control 失效
标题翻译：具有隐藏刷新控制的动态随机存取存储器
公开(公告)号：US4641281A
公开(公告)日：1987-02-03
申请号：US638675
申请日：1984-08-08
申请人： Koichiro Mashiko , Michihiro Yamada , Kazutami Arimoto , Hiroshi Miyamoto , Toshifumi Kobayashi , Yoshikazu Morooka
发明人： Koichiro Mashiko , Michihiro Yamada , Kazutami Arimoto , Hiroshi Miyamoto , Toshifumi Kobayashi , Yoshikazu Morooka
IPC分类号： G11C11/407 , G11C7/06 , G11C7/10 , G11C11/4091 , G11C7/00
CPC分类号： G11C7/106 , G11C11/4091 , G11C7/062 , G11C7/1051 , G11C7/1069
摘要： A dynamic random access memory that contains a memory cell array including a plurality of memory cells includes a pre-amplifier intended to amplify data which is read out from a memory cell accessed by an address signal; a main-amplifier intended to amplify the output of the pre-amplifier and output the amplified signal; and a driver circuit intended to output a driving signal for driving the main-amplifier, the driver circuit includes a first and a second transistor, wherein a drain of the first transistor is connected to a node corresponding to an output terminal of the driver circuit, with a source of the first transistor being earthed and with a gate thereof being connected to the drain of the second transistor, and wherein a gate of the second transistor is connected to the node with a source thereof being earthed.
摘要翻译：包含包括多个存储单元的存储单元阵列的动态随机存取存储器包括用于放大从由地址信号访问的存储单元读出的数据的前置放大器; 用于放大前置放大器的输出并输出放大信号的主放大器; 以及旨在输出用于驱动主放大器的驱动信号的驱动电路，所述驱动电路包括第一和第二晶体管，其中所述第一晶体管的漏极连接到对应于所述驱动器电路的输出端子的节点，其中第一晶体管的源极接地并且其栅极连接到第二晶体管的漏极，并且其中第二晶体管的栅极连接到节点，其源极接地。

25. 发明授权

US4855613A Wafer scale integration semiconductor device having improved chip power-supply connection arrangement 失效
标题翻译：具有改进的芯片电源连接布置的晶片级集成半导体器件
公开(公告)号：US4855613A
公开(公告)日：1989-08-08
申请号：US144383
申请日：1988-01-15
申请人： Michihiro Yamada , Hiroshi Miyamoto
发明人： Michihiro Yamada , Hiroshi Miyamoto
IPC分类号： H01L27/02
CPC分类号： H01L27/0218
摘要： A plurality of RAM chips, a V.sub.CC power supply terminal and a V.sub.SS power supply terminal are all formed on one wafer. Each of the RAM chips comprises an MOS circuit comprising a V.sub.CC power supply line and a V.sub.SS power supply line, a power supply terminal and a ground terminal. The ground terminal is connected to the V.sub.SS power supply line through an N channel MOS transistor, and the power supply terminal is connected to the V.sub.CC power supply line. The MOS transistor has a gate connected to a power supply terminal through a fuse element. The power supply terminals and the ground terminals in the plurality of RAM chips are connected to the V.sub.CC power supply terminal and the V.sub.SS power supply terminal, respectively, by aluminum interconnections. When a power-supply voltage is applied between the V.sub.CC power supply terminal and the V.sub.SS power supply terminal, the MOS transistor in each of the RAM chips is turned on, so that the power-supply voltage is supplied to the MOS circuit in each of the RAM chips. When a fuse element in any of the RAM chips is disconnected, the MOS transistor in the RAM chip is turned off, so that the power-supply voltage is not supplied to the MOS circuit in the RAM chip and the power-supply voltage is supplied to the MOS circuits in the other RAM chips.
摘要翻译：多个RAM芯片，VCC电源端子和VSS电源端子都形成在一个晶片上。每个RAM芯片包括包括VCC电源线和VSS电源线，电源端子和接地端子的MOS电路。接地端子通过N沟道MOS晶体管连接到VSS电源线，电源端子连接到VCC电源线。 MOS晶体管具有通过熔丝元件连接到电源端子的栅极。多个RAM芯片中的电源端子和接地端子分别通过铝互连连接到VCC电源端子和VSS电源端子。当在VCC电源端子和VSS电源端子之间施加电源电压时，每个RAM芯片中的MOS晶体管导通，使得电源电压被提供给MOS电路 RAM芯片。当任何RAM芯片中的熔断元件断开时，RAM芯片中的MOS晶体管被截止，使得电源电压不被提供给RAM芯片中的MOS电路并且提供电源电压到其他RAM芯片中的MOS电路。

26. 发明授权

US4788455A CMOS reference voltage generator employing separate reference circuits for each output transistor 失效
标题翻译： CMOS参考电压发生器为每个输出晶体管采用单独的参考电路
公开(公告)号：US4788455A
公开(公告)日：1988-11-29
申请号：US891897
申请日：1986-08-01
申请人： Shigeru Mori , Hiroshi Miyamoto , Tadato Yamagata , Michihiro Yamada , Kazutami Arimoto
发明人： Shigeru Mori , Hiroshi Miyamoto , Tadato Yamagata , Michihiro Yamada , Kazutami Arimoto
IPC分类号： G05F3/24
CPC分类号： G05F3/24
摘要： An internal power supply voltage generator for generating an internal power supply voltage for a semiconductor integrated device includes first and second reference voltage generators which produce first and second reference voltages having respective values a predetermined amount above and below an optimal value of the internal power supply voltage. The first and second reference voltage generators are constructed of a pair of serially connected NMOS and PMOS transistors, respectively, which transistors are connected between an external voltage supply and ground. The first and second reference voltages are applied to a CMOS output stage constructed of a NMOS and PMOS transistor serially connected between the external voltage supply and ground, the gates of the transistors being coupled to the first and second reference voltages, so as to provide said internal power supply voltage at a common node between the transistors. This voltage generator exhibits a lowered power dissipation and a lowered output impedance, as a result of providing a CMOS output stage.
摘要翻译：用于产生用于半导体集成器件的内部电源电压的内部电源电压发生器包括第一和第二参考电压发生器，其产生具有高于和低于内部电源电压的最佳值的预定量的相应值的第一和第二参考电压。第一和第二参考电压发生器分别由一对串联连接的NMOS和PMOS晶体管构成，这些晶体管连接在外部电压源和地之间。第一和第二参考电压被施加到由串联连接在外部电压源和地之间的NMOS和PMOS晶体管构成的CMOS输出级，晶体管的栅极耦合到第一和第二参考电压，以便提供所述在晶体管之间的公共节点处的内部电源电压。作为提供CMOS输出级的结果，该电压发生器具有降低的功率消耗和降低的输出阻抗。

27. 发明授权

US4689770A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4689770A
公开(公告)日：1987-08-25
申请号：US792071
申请日：1985-10-28
申请人： Hiroshi Miyamoto , Koichiro Mashiko , Toshifumi Kobayashi , Michihiro Yamada
发明人： Hiroshi Miyamoto , Koichiro Mashiko , Toshifumi Kobayashi , Michihiro Yamada
IPC分类号： G11C11/401 , G11C5/02 , G11C7/18 , G11C11/4097 , H01L21/8242 , H01L27/10 , H01L27/108 , G11C11/24
CPC分类号： G11C5/025 , G11C11/4097 , G11C7/18 , H01L2924/0002
摘要： An LSI semiconductor memory device in which errors in reading out memory cells connected to outermost bit lines of a memory cell array of the device are substantially eliminated. In accordance with the invention, this is done by making capacitances associated with the bit lines of respective ones of the memory cell array substantially equal to one another. To accomplish this, the configuration of an inside portion of wiring other than the bit lines of the array is made the same as that of the bit lines, and the distance between the outermost bit line and the other wiring is made equal to the distance between adjacent ones of the bit lines.
摘要翻译：基本上消除了读出连接到器件的存储单元阵列的最外位线的存储单元的错误的LSI半导体存储器件。根据本发明，这是通过使与存储单元阵列中相应的位线相关联的电容基本上彼此相等来实现的。为了实现这一点，使除阵列的位线之外的布线的内部部分的配置与位线的配置相同，并且使最外侧位线和其它布线之间的距离等于相邻的位线。

28. 发明授权

US09115661B2 Fuel injection amount control system and fuel injection amount control device for multi-cylinder internal combustion engine 有权
标题翻译：燃油喷射量控制系统和多缸内燃机燃油喷射量控制装置
公开(公告)号：US09115661B2
公开(公告)日：2015-08-25
申请号：US13194922
申请日：2011-07-30
申请人： Yasushi Iwazaki , Hiroshi Miyamoto
发明人： Yasushi Iwazaki , Hiroshi Miyamoto
IPC分类号： G06F7/00 , G06F17/00 , F02D41/30 , F02D41/14 , F02D41/24
CPC分类号： F02D41/1441 , F02D41/2493 , F02D2041/1432 , Y02T10/22
摘要： A fuel injection amount control system corrects the amount of fuel injected from each fuel injection valve in a feedback manner, based on an output value of an upstream air-fuel ratio sensor, so that the air-fuel ratio of exhaust gas flowing into a three-way catalyst coincides with a target air-fuel ratio. Also, the control system performs a high-pass filtering operation on the output value of the upstream air-fuel ratio sensor, so as to obtain a post-high-pass-filtering output value by removing a component that varies with variations in the center air-fuel ratio of the engine, from the output value of the upstream air-fuel ratio sensor. Then, the control system acquires an air-fuel ratio imbalance index value that increases as the degree of ununiformity in the air-fuel ratio among cylinders is larger, based on the post-high-pass-filtering output value.
摘要翻译：燃料喷射量控制系统基于上游空燃比传感器的输出值，以反馈方式校正从每个燃料喷射阀喷射的燃料量，使得流入三个燃料喷射量的排气的空燃比 - 催化剂与目标空燃比一致。此外，控制系统对上游空燃比传感器的输出值进行高通滤波操作，以便通过去除随中心变化而变化的分量来获得后高通滤波输出值发动机的空燃比从上游空燃比传感器的输出值。然后，控制系统基于后高通滤波输出值，获取随着气缸中的空燃比的不均匀程度越大而增加的空燃比不平衡指数值。

29. 发明授权

US08965665B2 Air-fuel ratio imbalance determining apparatus among cylinders for an internal combustion engine 有权
标题翻译：用于内燃机的气缸中的空燃比不平衡确定装置
公开(公告)号：US08965665B2
公开(公告)日：2015-02-24
申请号：US13389082
申请日：2009-08-06
申请人： Yasushi Iwazaki , Hiroshi Miyamoto , Fumihiko Nakamura , Hiroshi Sawada , Toru Kidokoro
发明人： Yasushi Iwazaki , Hiroshi Miyamoto , Fumihiko Nakamura , Hiroshi Sawada , Toru Kidokoro
IPC分类号： F02D41/22 , F02D41/00 , F02D41/14
CPC分类号： F02D41/008 , F02D41/1456
摘要： An air-fuel ratio imbalance among cylinders determining apparatus according to the present invention obtains an output Vabyfs of an air-fuel ratio sensor disposed at a portion downstream of an exhaust gas aggregated portion of an exhaust gas passage, and obtains a second-order differential value d2AF (a change rate of a change rate of a detected air-fuel ratio abyfs) of a detected air-fuel ratio abyfs represented by the air-fuel ratio sensor output Vabyfs. The imbalance determining apparatus determines that an air-fuel ratio imbalance state among cylinders is occurring when a detected air-fuel ratio second-order differential corresponding value (for example, a second-order differential value d2AF per se) obtained in accordance with the second-order differential value d2AF is larger than a first threshold value.
摘要翻译：根据本发明的气缸确定装置之间的空燃比不平衡获得设置在排气通道的排气集中部分下游的空燃比传感器的输出Vabyfs，并获得二阶微分由空燃比传感器输出Vabyfs表示的检测空燃比abyfs的值d2AF（检测空燃比abyfs的变化率的变化率）。不平衡确定装置确定当根据第二个所获得的检测到的空燃比二阶差分对应值（例如，二阶差分值d2AF本身）发生气缸之间的空燃比不平衡状态时 - 阶微分值d2AF大于第一阈值。

30. 发明授权

US08911610B2 Process for producing metallic lithium 有权
标题翻译：金属锂制造方法
公开(公告)号：US08911610B2
公开(公告)日：2014-12-16
申请号：US13608561
申请日：2012-09-10
申请人： Eiji Nakamura , Hiroaki Takata , Yukihiro Yokoyama , Hiroshi Miyamoto
发明人： Eiji Nakamura , Hiroaki Takata , Yukihiro Yokoyama , Hiroshi Miyamoto
IPC分类号： C25C3/02 , C01D15/04
CPC分类号： C01D15/04 , C25C3/02
摘要： Provided is a safe and efficient method for producing lithium metal which facilitates efficient production of anhydrous lithium chloride without corrosion of the system materials by chlorine gas or molten lithium carbonate, and which allows production of lithium metal by molten salt electrolysis of the produced anhydrous lithium chloride as a raw material. The method includes the steps of (A) contacting and reacting lithium carbonate and chlorine gas in a dry process to produce anhydrous lithium chloride, and (B) subjecting the raw material for electrolysis containing the anhydrous lithium chloride to molten salt electrolysis under such conditions as to produce lithium metal, wherein the chlorine gas generated by the molten salt electrolysis in step (B) is used as the chlorine gas in step (A) to continuously perform steps (A) and (B).
摘要翻译：提供了一种安全有效的生产锂金属的方法，其有助于无氯氯化物的有效生产，而不会由于氯气或熔融碳酸锂而使系统材料腐蚀，并且通过熔融盐电解生产无机氯化锂的锂金属作为原料。该方法包括以下步骤：（A）在干法中使碳酸锂和氯气接触并反应生成无水氯化锂;（B）将含有无水氯化锂的电解原料进行熔融盐电解，为了生产锂金属，其中在步骤（B）中通过熔融盐电解产生的氯气用作步骤（A）中的氯气，以连续进行步骤（A）和（B）。

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