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21. 发明申请

US20090039936A1 Flip-flop circuit, pipeline circuit including a flip-flop circuit, and method of operating a flip-flop circuit 有权
标题翻译：触发器电路，包括触发器电路的管线电路和操作触发器电路的方法
公开(公告)号：US20090039936A1
公开(公告)日：2009-02-12
申请号：US12222481
申请日：2008-08-11
申请人： Min-su Kim
发明人： Min-su Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/356139
摘要： Example embodiments relate to an electronic circuit, for example, a flip-flop circuit, a pipeline circuit including the flip-flop circuit and a method for operating the flip-flop circuit. A flip-flop circuit may include a precharge transistor configured to precharge an internal node to a first power supply voltage in response to a clock signal, a first pull-down unit configured to pull down a voltage of the internal node to a second power supply voltage, a pull-up transistor configured to pull up a voltage of an output node to the first power supply voltage in response to the voltage of the internal node, and a second pull-down unit configured to pull down the voltage of the output node to the second power supply voltage. The pipeline circuit may include a pulse generating circuit, a first flip-flop group, a combination logic circuit, and a second flip-flop group. A method for operating a flip-flop circuit may include precharging an internal node to a first power supply voltage in response to a clock signal, pulling down a voltage of the internal node, pulling down the voltage to a second power supply voltage in response to a first pulse signal, and pulling up a voltage of an output node to the first power supply voltage.
摘要翻译：示例性实施例涉及电子电路，例如触发器电路，包括触发器电路的流水线电路和用于操作触发器电路的方法。触发器电路可以包括预充电晶体管，其被配置为响应于时钟信号而将内部节点预充电到第一电源电压;第一下拉单元，被配置为将内部节点的电压下拉到第二电源电压，上拉晶体管，其被配置为响应于所述内部节点的电压将输出节点的电压上拉到所述第一电源电压;以及第二下拉单元，被配置为下拉所述输出节点的电压到第二个电源电压。流水线电路可以包括脉冲发生电路，第一触发器组，组合逻辑电路和第二触发器组。用于操作触发器电路的方法可以包括响应于时钟信号将内部节点预充电到第一电源电压，拉下内部节点的电压，响应于第二电源电压将电压拉低到第二电源电压第一脉冲信号，并将输出节点的电压提升到第一电源电压。

22. 发明申请

US20060085709A1 Flip flop circuit & same with scan function 有权
公开(公告)号：US20060085709A1
公开(公告)日：2006-04-20
申请号：US11239323
申请日：2005-09-30
申请人： Chung-hee Kim , Min-su Kim
发明人： Chung-hee Kim , Min-su Kim
IPC分类号： G01R31/28
CPC分类号： G01R31/318541 , H03K3/0375 , H03K17/693
摘要： A pulse-based flip flop, which outputs a scan input signal and a data signal, may include: a pulse generator to generate a pulse signal for coordinating operation of the flip flop; a multiplexer to receive the data signal, the scan input signal, and a scan enable signal, and to selectively output one of the data signal and the scan input signal in response to the scan enable signal; and a latch unit to transfer therethrough a signal received from the multiplexer according to the pulse signal.

23. 发明授权

US06586284B2 Silicon-on-insulator (SOI) substrate, method for fabricating SOI substrate and SOI MOSFET using the SOI substrate 失效
公开(公告)号：US06586284B2
公开(公告)日：2003-07-01
申请号：US10186509
申请日：2002-07-01
申请人： Min-su Kim
发明人： Min-su Kim
IPC分类号： H01L2100
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/84
摘要： The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications. Also, a variety of operational failures caused by the floating effect can be eliminated in die SOI substrate. As a consequence, additional effort is not required for designing or verifying the circuit of the present invention, so as to make it possible to construct a highly efficient, but low power consuming system.

24. 发明授权

US07999590B2 Level-converting flip-flop and pulse generator for clustered voltage scaling 有权
标题翻译：电平转换触发器和脉冲发生器，用于集群电压缩放
公开(公告)号：US07999590B2
公开(公告)日：2011-08-16
申请号：US12591668
申请日：2009-11-27
申请人： Min-su Kim
发明人： Min-su Kim
IPC分类号： H03K3/00
CPC分类号： H03K19/017509 , H03K3/037
摘要： Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch. Both the pulse generator and the flip-flop may have a level converting function without additional circuits, and therefore, the operating speeds of the pulse generator and the flip-flop may be increased without increasing the area and power consumption of the system.
摘要翻译：提供了用于集束电压缩放的电平转换触发器和用于触发器的电平转换脉冲发生器。触发器可以包括脉冲发生器，其接收具有等于第一电平的高电平的输入时钟信号，并产生具有高电平的脉冲信号，该高电平可被转换成高于第一电平的第二电平。触发器还可以包括锁存器，其锁存具有等于低于第二电平的第三电平的高电平的输入数据，并且响应于脉冲信号输出可以被转换成第二电平的高电平的输出数据。第三级可能等于第一级。可以将第二电平的电源电压用作锁存器的电源电压。脉冲发生器和触发器都可以具有电平转换功能而没有额外的电路，因此，可以增加脉冲发生器和触发器的工作速度，而不增加系统的面积和功耗。

25. 发明授权

US07881756B2 Level shifters and level shifting methods for suppressing current flow and generating fixed output values 有权
标题翻译：电平移位器和电平转换方法，用于抑制电流和产生固定输出值
公开(公告)号：US07881756B2
公开(公告)日：2011-02-01
申请号：US11708354
申请日：2007-02-21
申请人： Jin-soo Park , Min-su Kim
发明人： Jin-soo Park , Min-su Kim
IPC分类号： H04B1/38 , H04M1/00
CPC分类号： H03K3/35613
摘要： A level shifter includes a level shifting circuit which receives input signal from a function block and changes the voltage level of the input signal, to output an output signal; a current blocking circuit, which suppresses current flowing to the level shifting circuit in an input suppression mode in which power supplied to the function block is cut and deactivates the level shifting circuit; and an output control circuit, which controls the output signal of the level shifting circuit to have a direct current (DC) voltage level in the input suppression mode.
摘要翻译：电平移位器包括电平移位电路，其接收来自功能块的输入信号并改变输入信号的电压电平，以输出输出信号; 电流阻塞电路，其抑制在输入抑制模式中流向电平移位电路的电流，其中提供给功能块的功率被切断并且使电平移位电路停用; 以及输出控制电路，其控制电平移位电路的输出信号在输入抑制模式下具有直流（DC）电压电平。

26. 发明申请

US20090201069A1 LEVEL SHIFTING CIRCUIT 有权
标题翻译：水平移位电路
公开(公告)号：US20090201069A1
公开(公告)日：2009-08-13
申请号：US12208056
申请日：2008-09-10
申请人： Chung-hee Kim , Min-su Kim , Jin-soo Park
发明人： Chung-hee Kim , Min-su Kim , Jin-soo Park
IPC分类号： H03L5/00
CPC分类号： H03K19/00323 , H03K19/0016 , H03K19/018528
摘要： A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal.
摘要翻译：电平移位电路包括：包括多个信号传送单元的第一电平移位单元; 第一操作控制单元响应于钳位信号而使第一电平移位单元的一些信号传送单元失活; 与第一电平移位单元并联连接并包括多个信号传送单元的第二电平移位单元; 第二操作控制单元响应于所述钳位信号而使所述第二电平移位单元的一些信号传送单元失活; 连接到第一和第二电平移动单元的输出端的信号输出单元; 以及夹紧单元，其响应于所述夹紧信号将所述第一和第二电平移位单元的输出端固定到预定电压电平。

27. 发明授权

US07492203B2 High speed flip-flops and complex gates using the same 有权
公开(公告)号：US07492203B2
公开(公告)日：2009-02-17
申请号：US11926664
申请日：2007-10-29
申请人： Min-su Kim
发明人： Min-su Kim
IPC分类号： H03K3/00
CPC分类号： H03K3/012 , H03K3/356121 , H03K3/356191 , H03K19/20
摘要： In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal. A logic level of a second intermediate node between the fourth PMOS transistor and the fifth NMOS transistor is latched by a second latch. Accordingly, intermediate nodes of the flip-flops are connected to ground voltages via two NMOS transistors upon logic level switching, rather than three or more, so that the switching time of the device is shortened.

28. 发明申请

US20070188211A1 Level-converting flip-flop and pulse generator for clustered voltage scaling 审中-公开
标题翻译：电平转换触发器和脉冲发生器，用于集群电压缩放
公开(公告)号：US20070188211A1
公开(公告)日：2007-08-16
申请号：US11706318
申请日：2007-02-15
申请人： Min-su Kim
发明人： Min-su Kim
IPC分类号： G06F1/04
CPC分类号： H03K19/017509 , H03K3/037
摘要： Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high level that may be converted into a second level higher than the first level. The flip-flop may further include a latch that latches input data with a high level equal to a third level lower than the second level and outputs output data with a high level that may be converted into the second level in response to the pulse signal. The third level may be equal to the first level. A supply voltage of the second level may be used as a supply voltage to the latch. Both the pulse generator and the flip-flop may have a level converting function without additional circuits, and therefore, the operating speeds of the pulse generator and the flip-flop may be increased without increasing the area and power consumption of the system.
摘要翻译：提供了用于集束电压缩放的电平转换触发器和用于触发器的电平转换脉冲发生器。触发器可以包括脉冲发生器，其接收具有等于第一电平的高电平的输入时钟信号，并产生具有高电平的脉冲信号，该高电平可被转换成高于第一电平的第二电平。触发器还可以包括锁存器，其锁存具有等于低于第二电平的第三电平的高电平的输入数据，并且响应于脉冲信号输出可以被转换成第二电平的高电平的输出数据。第三级可能等于第一级。可以将第二电平的电源电压用作锁存器的电源电压。脉冲发生器和触发器都可以具有电平转换功能而没有额外的电路，因此，可以增加脉冲发生器和触发器的工作速度，而不增加系统的面积和功耗。

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