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21. 发明授权

US08136010B2 Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs 失效
标题翻译：具有多个中间输出的流水线循环冗余校验电路的装置
公开(公告)号：US08136010B2
公开(公告)日：2012-03-13
申请号：US11962878
申请日：2007-12-21
申请人： Todd E. Leonard , Gregory J. Mann
发明人： Todd E. Leonard , Gregory J. Mann
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6575
摘要： A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.
摘要翻译：提出了一种CRC冗余计算电路和包括体现在机器可读介质中的电路的设计结构。 CRC冗余计算电路被流水线运行，并以配置为在数据包的基本粒度的任意倍数上运行。此外，CRC冗余计算电路提供了提供中间输出余数值的相同倍数的输出。因此，例如，每个周期处理24字节分组数据并且分组具有4字节粒度的电路，CRC冗余计算电路提供6个输出余数值，每个4字节数据片段一个。

22. 发明申请

US20090089472A1 Program memory test access collar 有权
标题翻译：程序记忆测试访问项圈
公开(公告)号：US20090089472A1
公开(公告)日：2009-04-02
申请号：US11906153
申请日：2007-09-28
申请人： Gregory J. Mann , Robert S. Hoffman
发明人： Gregory J. Mann , Robert S. Hoffman
IPC分类号： G06F13/24
CPC分类号： G06F13/4243
摘要： A memory access device includes logic to switch data from a processor memory bus to a memory bus in a first operational mode, and to switch data from a test bus to the memory bus in a second operational mode, and logic to switch address signals from the processor memory bus to the memory bus in the first operational mode. In the second operational mode the device accepts from the test bus a starting memory address for memory reads and writes, and automatically and independently of the test bus adjusts a memory address for reads and writes during burst memory operations.
摘要翻译：存储器访问装置包括在第一操作模式中将数据从处理器存储器总线切换到存储器总线的逻辑，以及在第二操作模式下将数据从测试总线切换到存储器总线的逻辑，以及用于切换来自处理器内存总线在第一个操作模式下到存储器总线。在第二种操作模式下，器件从测试总线接收存储器读写的起始存储器地址，并且自动和独立于测试总线在突发存储器操作期间调整读取和写入的存储器地址。

23. 发明授权

US07254647B2 Network for decreasing transmit link layer core speed 失效
标题翻译：降低传输链路层内核速度的网络
公开(公告)号：US07254647B2
公开(公告)日：2007-08-07
申请号：US09816967
申请日：2001-03-23
申请人： Gregory J. Mann
发明人： Gregory J. Mann
IPC分类号： G06F15/173 , G06F5/00 , G06F13/12
CPC分类号： G06F13/4059
摘要： A processor includes a core for providing speed reduction in communications between a transmission media and a processor having an upper link layer in a parallel-serial architecture. The core includes a lower logic layer, serial lanes connecting the logic layer to the transmission media, at least one selector connected to the serial lanes for supporting at least two differing data widths. The logic layer controls the selector, and multiple buffers are interposed in the serial lanes. The selector enables the speed reductions is the upper link layer of the processor. The processor is particularly applicable to interface components used in InfiniBand-type hardware.
摘要翻译：处理器包括用于在传输介质和具有并行串行架构中的上链路层的处理器之间的通信中提供速度降低的核心。核心包括下层逻辑层，将逻辑层连接到传输介质的串行通道，连接到串行通道的至少一个选择器，用于支持至少两个不同的数据宽度。逻辑层控制选择器，并且多个缓冲器插入到串行通道中。选择器使速度降低是处理器的上链路层。处理器特别适用于InfiniBand型硬件中使用的接口组件。

24. 发明授权

US07225387B2 Multilevel parallel CRC generation and checking circuit 失效
标题翻译：多级并行CRC生成和检查电路
公开(公告)号：US07225387B2
公开(公告)日：2007-05-29
申请号：US10771823
申请日：2004-02-03
申请人： Ming-i M. Lin , Brian J. Connolly , Todd E. Leonard , Gregory J. Mann , Jonathan H. Raymond
发明人： Ming-i M. Lin , Brian J. Connolly , Todd E. Leonard , Gregory J. Mann , Jonathan H. Raymond
IPC分类号： H03M13/00
CPC分类号： H03M13/091
摘要： A CRC generator/checker for generating CRC results, comprising: a set of CRC circuits connected in series, each CRC circuit responsive to a different control signal generated by a control logic, each CRC circuit having a seed input adapted to receive a seed, a data input adapted to receive and process a different set of M-bits of a data unit and a result output adapted to generate a result, the result output of a previous CRC circuit connected to the seed input of an immediately subsequent CRC circuit, the seed input of a first CRC circuit connected to an output of a remainder register, an input of the remainder register connected to an output of a multiplexer, the result outputs of the multiplicity of CRC circuits connected to different inputs of the multiplexer, the multiplexer responsive to a select signal generated by the control logic.
摘要翻译：一种用于产生CRC结果的CRC发生器/检验器，包括：串联连接的一组CRC电路，每个CRC电路响应于由控制逻辑产生的不同的控制信号，每个CRC电路具有适于接收种子的种子输入，数据输入，适于接收和处理数据单元的不同的M位组，以及适于产生结果的结果输出，连接到紧接着的CRC电路的种子输入的先前CRC电路的结果输出，种子连接到余数寄存器的输出的第一CRC电路的输入，连接到多路复用器的输出的剩余寄存器的输入，结果连接到多路复用器的不同输入的多个CRC电路的输出，多路复用器响应于由控制逻辑产生的选择信号。

25. 发明授权

US5322659A Method for rendering a substrate surface antithrombogenic and/or anti-infective 失效
标题翻译：用于使底物表面抗血栓形成和/或抗感染的方法
公开(公告)号：US5322659A
公开(公告)日：1994-06-21
申请号：US586115
申请日：1990-09-21
申请人： Anthony J. Walder , Donald D. Solomon , Gregory J. Mann
发明人： Anthony J. Walder , Donald D. Solomon , Gregory J. Mann
IPC分类号： A61L27/54 , A61L29/16 , A61L33/00 , B29C47/06 , B32B37/00
CPC分类号： A61L33/0041 , A61L27/54 , A61L29/16 , A61L33/0023 , B29C47/0016 , B29C47/0023 , B29C47/065 , A61L2300/404 , A61L2300/406 , A61L2300/42 , A61L2300/45 , B29C47/0026 , B29C47/06 , B29K2023/06 , B29K2023/12 , B29K2025/00 , B29K2027/06 , B29K2033/04 , B29K2067/00 , B29K2075/00 , B29K2077/00 , B29K2105/0011 , B29K2995/0092 , B29K2995/0093 , B29L2023/22
摘要： A method to render a medical article antithrombogenic and/or anti-infective includes coextruding a base polymer with a hydrophilic laminating polymer having dispersed therein a quarternary salt complexing agent and steeping the extruded article in an aqueous solution of an antithrombogenic and/or anti-infective reagent whereby the reagent is absorbed along with water by the hydrophilic polymer and reacts with the complexing agent.
摘要翻译：使医疗制品抗血栓形成和/或抗感染的方法包括将基础聚合物与其中分散有季盐络合剂的亲水层压聚合物共挤出，并将挤出制品浸入抗血栓形成和/或抗感染的水溶液中试剂，其中试剂与水一起被亲水性聚合物吸收并与络合剂反应。

26. 发明授权

US08866654B2 Apparatus for analog-to-digital conversion with a high effective-sample-rate on the leading edge of a signal pulse 有权
标题翻译：用于在信号脉冲前沿具有高有效采样率的模数转换的装置
公开(公告)号：US08866654B2
公开(公告)日：2014-10-21
申请号：US13091928
申请日：2011-04-21
申请人： Gregory J. Mann , Gin-Chung Wang
发明人： Gregory J. Mann , Gin-Chung Wang
IPC分类号： H03M1/00 , G01T1/17 , H03M1/12
CPC分类号： G01T1/17 , H03M1/00 , H03M1/12 , H03M2201/4233
摘要： A method and electronic device for outputting time values and energy of an analog input signal by dynamically determining a plurality of threshold values, comparing, using a plurality of comparator circuits, the plurality of threshold values against the analog input signal, outputting, using at least one time to digital conversion circuit connected to each of the plurality of comparator circuits, a plurality of time values, each time value output when the analog input signal meets or exceeds a threshold value of the threshold values, filtering the analog input signal, performing, using an analog-to-digital conversion circuit, analog-to-digital conversion of the filtered analog input signal to generate a digital signal, and calculating, in response to receiving a trigger signal, an energy of the digital signal.
摘要翻译：一种用于通过动态地确定多个阈值来输出模拟输入信号的时间值和能量的方法和电子装置，使用多个比较器电路比较多个阈值与模拟输入信号的比较，至少使用连接到多个比较器电路中的每一个的一次数字转换电路，多个时间值，当模拟输入信号达到或超过阈值的阈值时输出每个时间值，对模拟输入信号进行滤波，使用模数转换电路，对经过滤波的模拟输入信号进行模数转换以产生数字信号，以及响应于接收到触发信号计算数字信号的能量。

27. 发明授权

US07886210B2 Apparatus for pipelined cyclic redundancy check circuit with multiple intermediate outputs 失效
标题翻译：具有多个中间输出的流水线循环冗余校验电路的装置
公开(公告)号：US07886210B2
公开(公告)日：2011-02-08
申请号：US11673086
申请日：2007-02-09
申请人： Todd E. Leonard , Gregory J. Mann
发明人： Todd E. Leonard , Gregory J. Mann
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/09
摘要： A CRC redundancy calculation circuit is presented which is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.
摘要翻译：提出了一种CRC冗余计算电路，其被流水线运行，并且被配置为在数据分组的基本粒度的任意倍数上操作。此外，CRC冗余计算电路提供了提供中间输出余数值的相同倍数的输出。因此，例如，每个周期处理24字节分组数据并且分组具有4字节粒度的电路，CRC冗余计算电路提供6个输出余数值，每个4字节数据片段一个。

28. 发明申请

US20090164865A1 APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIPLE INTERMEDIATE OUTPUTS 失效
标题翻译：用于管道循环冗余的装置用多个中间输出检查电路
公开(公告)号：US20090164865A1
公开(公告)日：2009-06-25
申请号：US11962878
申请日：2007-12-21
申请人： Todd E. Leonard , Gregory J. Mann
发明人： Todd E. Leonard , Gregory J. Mann
IPC分类号： H03M13/15 , G06F11/10
CPC分类号： H03M13/091 , H03M13/6575
摘要： A CRC redundancy calculation circuit and a design structure including the circuit embodied in a machine readable medium are presented. The CRC redundancy calculation circuit is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.
摘要翻译：提出了一种CRC冗余计算电路和包括体现在机器可读介质中的电路的设计结构。 CRC冗余计算电路被流水线运行在高频率并被配置为在数据分组的基本粒度的任意倍数上操作。此外，CRC冗余计算电路提供了提供中间输出余数值的相同倍数的输出。因此，例如，每个周期处理24字节分组数据并且分组具有4字节粒度的电路，CRC冗余计算电路提供6个输出余数值，每个4字节数据片段一个。

29. 发明申请

US20080195915A1 APPARATUS FOR PIPELINED CYCLIC REDUNDANCY CHECK CIRCUIT WITH MULTIPLE INTERMEDIATE OUTPUTS 失效
标题翻译：用于管道循环冗余的装置用多个中间输出检查电路
公开(公告)号：US20080195915A1
公开(公告)日：2008-08-14
申请号：US11673086
申请日：2007-02-09
申请人： Todd E. Leonard , Gregory J. Mann
发明人： Todd E. Leonard , Gregory J. Mann
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/09
摘要： A CRC redundancy calculation circuit is presented which is pipelined to run at high frequencies and configured to operate on an arbitrary multiple of the base granularity of the data packet. Additionally, the CRC redundancy calculation circuit provides the same multiple of outputs that provide intermediary output remainder values. Thus, for example, a circuit which processes 24 bytes of packet data per cycle and which the packets have a 4 byte granularity, the CRC redundancy calculation circuit provides 6 output remainder values, one for each 4 byte slice of data.
摘要翻译：提出了一种CRC冗余计算电路，其被流水线运行，并且被配置为在数据分组的基本粒度的任意倍数上操作。此外，CRC冗余计算电路提供了提供中间输出余数值的相同倍数的输出。因此，例如，每个周期处理24字节分组数据并且分组具有4字节粒度的电路，CRC冗余计算电路提供6个输出余数值，每个4字节数据片段一个。

30. 发明授权

US07328396B2 Cyclic redundancy check generating circuit 有权
标题翻译：循环冗余校验生成电路
公开(公告)号：US07328396B2
公开(公告)日：2008-02-05
申请号：US10709794
申请日：2004-05-28
申请人： Gregory J. Mann
发明人： Gregory J. Mann
IPC分类号： H03M13/00
CPC分类号： H03M13/091 , H03M13/6572
摘要： A circuit, a method, and a method of designing the circuit, the circuit including: multiple W-bit packet data slice latches; a data partition comprising multiple data XOR subtree levels and having data latches between the data XOR subtree levels; a remainder partition comprising multiple remainder XOR subtree levels and having remainder latches between the remainder XOR subtree levels; a combinatorial XOR tree, outputs of the remainder partition and outputs of the data partition connected to inputs of the combinatorial XOR tree; and a remainder latch, combinatorial XOR tree connected to the remainder latch and the outputs of the remainder latch connected to the remainder partition.
摘要翻译：一种设计电路的电路，方法和方法，所述电路包括：多个W位分组数据片锁存器; 数据分区，包括多个数据XOR子树级别，并且在数据XOR子树级之间具有数据锁存器; 剩余分区包括多个余数XOR子树级别，并且在余数XOR子树级别之间具有余数锁存器; 组合XOR树，连续到组合XOR树的输入的数据分区的剩余分区和输出的输出; 以及连接到剩余锁存器的剩余锁存组合XOR树，并且剩余锁存器的输出连接到其余分区。

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