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21. 发明申请

US20070140017A1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20070140017A1
公开(公告)日：2007-06-21
申请号：US11637026
申请日：2006-12-12
申请人： Seiji Kaneko , Naoki Ueda
发明人： Seiji Kaneko , Naoki Ueda
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/3454 , G11C11/5628 , G11C11/5635 , G11C16/3404 , G11C16/3409 , G11C16/3413 , G11C16/344 , G11C16/3445 , G11C16/3459 , G11C2211/5621
摘要： There is provided a nonvolatile semiconductor memory device capable of accelerating writing time and avoiding readout errors of information by eliminating variation in threshold voltage of unselected memory cells. In a nonvolatile semiconductor memory device having a memory cell array with memory cells capable of erasing and programming information, the memory cells store one data value selected from the same number of data values as programming distribution ranges, associated with that the electrical attribute belongs to any one of the more than one programming distribution ranges. The device comprises an erasure means for erasing the selected memory cell to be erased so that its electrical attribute belongs to a erasure distribution range not overlapping any of the programming distribution ranges and a programming means for programming an erased memory cell to be programmed so that its electrical attribute belongs to any one of the programming distribution ranges.
摘要翻译：提供一种非易失性半导体存储器件，其能够通过消除未选择的存储单元的阈值电压的变化来加速写入时间并避免信息的读出错误。在具有具有能够擦除和编程信息的存储器单元的存储单元阵列的非易失性半导体存储器件中，存储器单元存储从与电属性属于任何相关联的编程分配范围相同数量的数据值中选择的一个数据值多个编程分布范围之一。该装置包括擦除装置，用于擦除被擦除的所选择的存储单元，使得其电属性属于不与任何编程分布范围重叠的擦除分布范围，以及编程装置，用于对要编程的擦除存储器单元进行编程，电属性属于编程分布范围中的任何一个。

22. 发明申请

US20070097724A1 Nonvolatile semiconductor memory device and its writing method 失效
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：US20070097724A1
公开(公告)日：2007-05-03
申请号：US11592043
申请日：2006-11-01
申请人： Masahiro Tomida , Naoki Ueda
发明人： Masahiro Tomida , Naoki Ueda
IPC分类号： G11C5/06
CPC分类号： G11C8/08 , G11C7/22 , G11C16/10
摘要： A nonvolatile semiconductor memory device and its writing method for reducing a writing rate variation without changing a voltage condition applied for each memory cell in writing operation is provided. The device comprises a memory cell array configuration where each drain of the memory cells on the same column is connected to a first bit line via a second bit line and a bit line contact, and the shortest distance from each drain of the memory cells to the bit line contact varies according to a location of the memory cell in the column direction. The method includes a writing operation carried out sequentially from the nearest memory cell to the bit line contact, upon writing continuously so that the memory cell current becomes small for all or some of the memory cells on the same column between the two adjacent bit line contacts in the column direction.
摘要翻译：提供了一种非易失性半导体存储器件及其写入方法，用于在不改变在写入操作中对每个存储单元施加的电压条件的同时降低写入速率变化。该器件包括存储单元阵列配置，其中同一列上的存储器单元的每个漏极经由第二位线和位线接触连接到第一位线，以及从存储器单元的每个漏极到第一位线的最短距离位线接触根据存储单元在列方向上的位置而变化。该方法包括在连续写入时从最近的存储单元顺序执行的写入操作，使得存储单元电流对于两个相邻位线触点之间的同一列上的所有或一些存储单元的电流变小在列方向。

23. 发明授权

US07107680B2 Manufacturing method of heat exchanger and structure thereof 有权
标题翻译：热交换器的制造方法及其结构
公开(公告)号：US07107680B2
公开(公告)日：2006-09-19
申请号：US10869726
申请日：2004-06-16
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： B23P15/26 , F28F3/12 , B23K31/02
CPC分类号： F28F3/025 , B23K1/0012 , B23K2101/14 , F28D1/0316 , F28D1/0535 , F28D2021/0082 , F28F2275/04 , Y10T29/49391 , Y10T29/49393
摘要： A first plate and a second plate have brazing paste on the surface thereof. When the first plate is combined with the second plate while an inner fin is disposed therein, a protrusion forms a clearance there between. Heat is added to evaporate the organic substances in the brazing paste. The organic substances vapor is discharged into outside of the tube through the clearance. After that, heat is added furthermore to melt the brazing paste. The first plate and the second plate are brazed together to form the tube and the inner fin is brazed to the inside of the tube.
摘要翻译：第一板和第二板在其表面上具有钎焊膏。当第一板与第二板组合而内部翅片设置在其中时，突起在其间形成间隙。添加热量以蒸发钎焊膏中的有机物质。有机物质蒸汽通过间隙排出管外。之后，加入热量以熔化钎焊膏。第一板和第二板钎焊在一起以形成管，并且内翅片钎焊到管的内部。

24. 发明申请

US20060083073A1 Method for setting erasing pulse and screening erasing defect of nonvolatile memory 有权
标题翻译：擦除脉冲设置方法和非易失性存储器屏蔽擦除缺陷的方法
公开(公告)号：US20060083073A1
公开(公告)日：2006-04-20
申请号：US11251453
申请日：2005-10-14
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： G11C16/04
CPC分类号： G11C16/3445 , G11C16/16 , G11C16/344 , G11C16/349
摘要： Method for determining the number of applications of erasing pulses, memory cells comprises, extracting two pairs of the accumulated number of the erasing pulses Np and the ratio Re of the number of erased memory cells in the target block to be erased after the accumulated number of the erasing pulses Np has been applied, converting the two ratios Re into normalized variables S(Re) through normalizing the random variables of the normal distribution probability with standard deviations, converting the two accumulated numbers of the erasing pulses Np into common logarithms Log(Np), calculating a common logarithm Log(Nt) through extrapolating from two sets of coordinates [Log(Np), S(Re)], and determining the number of applications of the remaining erasing pulses so that the extrapolation erasing pulse number Nt is the target accumulated number of applications of erasing pulses.
摘要翻译：用于确定擦除脉冲的应用次数的方法，存储器单元包括：提取两对累积数量的擦除脉冲Np，以及在累积数量的擦除脉冲数目的累积数量之后提取要擦除的目标块中的擦除存储器单元数量的比率Re 已经施加了擦除脉冲Np，通过用标准偏差标准化正态分布概率的随机变量将两个比率Re转换成归一化变量S（Re），将擦除脉冲Np的两个累加数转换为通用对数Log（Np ），通过从两组坐标[Log（Np），S（Re）]进行外推来计算通常的对数Log（Nt），并且确定剩余擦除脉冲的应用次数，使得外插擦除脉冲数Nt为目标累计擦除脉冲数。

25. 发明授权

US06916709B2 Non-volatile semiconductor memory device and manufacturing method for the same 有权
标题翻译：非易失性半导体存储器件及其制造方法相同
公开(公告)号：US06916709B2
公开(公告)日：2005-07-12
申请号：US10732444
申请日：2003-12-11
申请人： Tadahiro Omi , Naoki Ueda
发明人： Tadahiro Omi , Naoki Ueda
IPC分类号： C23C16/34 , C23C16/40 , C23C16/511 , H01L21/28 , H01L21/318 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11531
摘要： A non-volatile semiconductor memory device comprising: a first insulating film provided on a silicon based substrate; a first electrode provided on the first insulating film as a floating gate; a second insulating film provided on the first electrode; and a second electrode formed as a control gate on the first electrode through the second insulating film, wherein the first insulating film is formed of at least two layers of: a lower silicon nitride film obtained by nitriding the silicon based substrate; and an upper silicon nitride film or upper silicon oxide film formed on the lower silicon nitride film according to a chemical vapor deposition method, and the lower silicon nitride film contains rare gas elements at an area density of 1010 cm−2 or more in at least a part of the lower silicon nitride film.
摘要翻译：一种非易失性半导体存储器件，包括：设置在硅基衬底上的第一绝缘膜; 设置在作为浮动栅极的第一绝缘膜上的第一电极; 设置在第一电极上的第二绝缘膜; 以及通过所述第二绝缘膜在所述第一电极上形成作为控制栅极的第二电极，其中所述第一绝缘膜由至少两层形成：通过氮化所述硅基衬底而获得的下部氮化硅膜; 以及根据化学气相沉积法形成在下部氮化硅膜上的上部氮化硅膜或上部氧化硅膜，并且下部氮化硅膜包含10 10的区域密度的稀有气体元素，在下部氮化硅膜的至少一部分中具有≥2以上的厚度。

26. 发明授权

US06621118B2 MOSFET, semiconductor device using the same and production process therefor 失效
标题翻译： MOSFET，使用相同的半导体器件及其制造工艺
公开(公告)号：US06621118B2
公开(公告)日：2003-09-16
申请号：US10202080
申请日：2002-07-25
申请人： Masanori Ohara , Naoki Ueda
发明人： Masanori Ohara , Naoki Ueda
IPC分类号： H01L2176
CPC分类号： H01L29/66484 , H01L21/823487 , H01L29/66621 , H01L29/7831 , H01L29/7834
摘要： A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is buried in the trench, and which generates an output by AND logic in response to inputs to the gate electrode and the trench gate electrode, wherein an impurity concentration directly below the gate electrode is higher than an impurity concentration directly below the trench gate electrode.
摘要翻译：一种MOSFET包括：第一导电类型，具有在其表面区域中形成的沟槽的半导体衬底，形成在半导体衬底上的栅电极; 以及沟槽栅电极，其与栅电极相邻并被埋在沟槽中，并且响应于对栅电极和沟槽栅电极的输入而由AND逻辑产生输出，其中在栅电极正下方的杂质浓度高于沟槽栅电极正下方的杂质浓度。

27. 发明授权

US4816332A Porous molded product and process for preparing the same 失效
标题翻译：多孔成型产品及其制备方法
公开(公告)号：US4816332A
公开(公告)日：1989-03-28
申请号：US181541
申请日：1988-04-14
申请人： Naoshi Fujita , Motoaki Oe , Hitoshi Yoshida , Yukihisa Takeuchi , Naoki Ueda
发明人： Naoshi Fujita , Motoaki Oe , Hitoshi Yoshida , Yukihisa Takeuchi , Naoki Ueda
IPC分类号： C08J9/36 , B29C44/56 , F24F3/16 , B32B3/26
CPC分类号： B29C44/5672 , B29C44/56 , B29C44/5618 , B29K2075/00 , B29L2028/00 , B29L2031/14 , Y10T428/249953 , Y10T428/249955 , Y10T428/249958 , Y10T428/249962 , Y10T428/249964 , Y10T428/249975
摘要： Disclosed are a porous molded product comprising a foam having a three-dimensional cell-membrane-free network skeletal structure, which has been extended to make long the shape of the mesh pores thereof in a given direction, and having deposited onto the skeleton thereof a cured resin without clogging the mesh pores and a process for preparing said porous molded product. The porous molded product according to this invention can be used as a filter material or used when a porous ceramic structural body is sinter molded.
摘要翻译：公开了一种多孔模制产品，其包括具有三维无细胞网络骨架结构的泡沫，其已经延伸以使其在给定方向上的网孔的形状长，并且沉积在其骨架上固化树脂，而不堵塞网孔，以及制备所述多孔模制产品的方法。根据本发明的多孔模制产品可以用作过滤材料，或者当多孔陶瓷结构体被烧结成型时使用。

28. 发明授权

US08610197B2 Nonvolatile memory having gate electrode and charge storage layer formed respectively over opposite surfaces of semiconductor layer 有权
标题翻译：具有分别形成在半导体层的相对表面上的栅电极和电荷存储层的非易失性存储器
公开(公告)号：US08610197B2
公开(公告)日：2013-12-17
申请号：US13201584
申请日：2009-12-14
申请人： Naoki Ueda , Yoshimitsu Yamauchi
发明人： Naoki Ueda , Yoshimitsu Yamauchi
IPC分类号： H01L29/786 , H01L29/788
CPC分类号： H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/7881
摘要： Provided is a nonvolatile memory 10 having a selective gate SG formed below a silicon layer 14, which is to be a channel region formed between a source region S and a drain region D of a transistor, through a gate insulating film 15 between the silicon layer and the selective gate, a floating gate FG formed on a part over the silicon layer 14 through a gate insulating film 16, and a control gate CG connected to the floating gate FG. The selective gate SG has one end overlapping the source region S through the gate insulating film 15, and the floating gate FG has one end overlapping the drain region D through the gate insulating film 16, and the other end separated from the source region S and overlapping the silicon layer 14 through the gate insulating film 16. Thus, a nonvolatile memory whose performance is not deteriorated even when it is formed on an insulating substrate having a low heat dissipating characteristic can be achieved.
摘要翻译：提供了一种非易失性存储器10，其具有形成在作为在晶体管的源极区域S和漏极区域D之间形成的沟道区域的硅层14下方的选择栅极SG，通过硅层之间的栅极绝缘膜15 选择栅极，通过栅极绝缘膜16形成在硅层14上的部分上的浮置栅极FG，以及连接到浮置栅极FG的控制栅极CG。选择栅极SG的一端通过栅极绝缘膜15与源极区域S重叠，并且浮置栅极FG的一端通过栅极绝缘膜16与漏极区域D重叠，另一端与源极区域S分离，通过栅极绝缘膜16与硅层14重叠。因此，即使在具有低散热特性的绝缘基板上形成性能也不会劣化的非易失性存储器。

29. 发明申请

US20120231374A1 BIPOLAR PLATE FOR FUEL CELL AND METHOD FOR PRODUCING THE SAME 有权
标题翻译：用于燃料电池的双极板及其制造方法
公开(公告)号：US20120231374A1
公开(公告)日：2012-09-13
申请号：US13511175
申请日：2010-12-24
申请人： Takashi Iseki , Kazuyuki Nakanishi , Yasuhiro Ozawa , Yuka Yamada , Hajime Hasegawa , Masafumi Koizumi , Katsutoshi Fujisawa , Naoki Ueda , Hirohiko Hisano
发明人： Takashi Iseki , Kazuyuki Nakanishi , Yasuhiro Ozawa , Yuka Yamada , Hajime Hasegawa , Masafumi Koizumi , Katsutoshi Fujisawa , Naoki Ueda , Hirohiko Hisano
IPC分类号： H01M8/02 , C23C16/503
CPC分类号： C01B31/02 , B82Y30/00 , C01B32/05 , H01M8/021 , H01M8/0228 , H01M8/0234 , Y02P70/56
摘要： A bipolar plate for a fuel cell comprises a substrate formed of stainless steel; an oriented amorphous carbon film formed at least on a surface of the substrate facing an electrode, and containing C as a main component, 3 to 20 at. % of N, and more than 0 at. % and not more than 20 at. % of H, and when the total amount of the C is taken as 100 at. %, the amount of C having an sp2 hybrid orbital (Csp2) being not less than 70 at. % and less than 100 at. %, and (002) planes of graphite being oriented along a thickness direction; a mixed layer generated in an interface between the substrate and the oriented amorphous carbon film and containing at least one kind of constituent atoms of each of the substrate and the oriented amorphous carbon film; and a plurality of projections protruding from the mixed layer into the oriented amorphous carbon film and having a mean length of 10 to 150 nm.
摘要翻译：用于燃料电池的双极板包括由不锈钢形成的基板; 至少在面向电极的基板的表面上形成并含有C为主要成分的定向非晶碳膜，3至20at。 N的百分比，超过0。％，不超过20。 H的百分比，当C的总量取为100时。％，具有sp2混合轨道（Csp2）的C的量不小于70at。％和小于100。％和（002）面的石墨沿厚度方向取向; 在所述基板和所述取向非晶碳膜之间的界面中产生并且含有所述基板和所述取向非晶碳膜中的至少一种构成原子的混合层; 以及从混合层突出到取向非晶碳膜中并具有10〜150nm的平均长度的多个突起。

30. 发明申请

US20100289675A1 Method of transforming geographic coordinate 有权
标题翻译：变换地理坐标的方法
公开(公告)号：US20100289675A1
公开(公告)日：2010-11-18
申请号：US12010924
申请日：2008-01-31
申请人： Naoki Ueda
发明人： Naoki Ueda
IPC分类号： H03M7/02
CPC分类号： G09B29/10 , G01C21/20 , G09B29/00
摘要： A method of transforming a geographic coordinate to a geographic location code includes the steps of: retrieving a latitude value and a longitude value of the geographic coordinate; quantizing the latitude value to a first integer value; quantizing the longitude value to a second integer value; converting the first integer value to a first code string, said first code string including a first digit representing a non-numeric character, a second digit representing a non-numeric character, and a third digit representing a numeric character; converting the second integer value to a second code string, said second code string including a fourth digit representing a non-numeric character, a fifth digit representing a non-numeric character, and a sixth digit representing a numeric character; and combining the first code string and the second code string to obtain the geographic location code having a fixed pattern of radix in a mixed radix notation system representation.
摘要翻译：将地理坐标变换为地理位置码的方法包括以下步骤：检索地理坐标的纬度值和经度值; 将纬度值量化为第一个整数值; 将经度值量化为第二整数值; 将所述第一整数值转换为第一代码串，所述第一代码串包括表示非数字字符的第一数字，表示非数字字符的第二数字和表示数字字符的第三数字; 将所述第二整数值转换为第二代码串，所述第二代码串包括表示非数字字符的第四数字，表示非数字字符的第五数字和表示数字字符的第六数字; 以及组合所述第一代码串和所述第二代码串，以获得具有固定模式的基数的地理位置代码。

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