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21. 发明授权

US09412709B2 Semiconductor structure with sacrificial anode and passivation layer and method for forming 有权
标题翻译：具有牺牲阳极和钝化层的半导体结构及其形成方法
公开(公告)号：US09412709B2
公开(公告)日：2016-08-09
申请号：US13898949
申请日：2013-05-21
申请人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
发明人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
IPC分类号： H01L21/56 , H01L21/44 , H01L23/00 , H01L23/31
CPC分类号： H01L24/02 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0218 , H01L2224/0219 , H01L2224/03005 , H01L2224/03009 , H01L2224/03015 , H01L2224/03019 , H01L2224/034 , H01L2224/03622 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2224/05565 , H01L2224/05567 , H01L2224/05624 , H01L2224/131 , H01L2224/13147 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/48463 , H01L2224/48507 , H01L2224/48824 , H01L2224/73265 , H01L2924/01012 , H01L2924/01029 , H01L2924/0103 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/365 , H01L2924/3651 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
摘要翻译：通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

22. 发明申请

US20140346663A1 SEMICONDUCTOR STRUCTURE WITH SACRIFICIAL ANODE AND METHOD FOR FORMING 有权
标题翻译：具有阳离子阳极的半导体结构和形成方法
公开(公告)号：US20140346663A1
公开(公告)日：2014-11-27
申请号：US13898949
申请日：2013-05-21
申请人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
发明人： Sheila F. Chopin , Min Ding , Varughese Mathew , Scott S. Roth
IPC分类号： H01L23/00
CPC分类号： H01L24/02 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0218 , H01L2224/0219 , H01L2224/03005 , H01L2224/03009 , H01L2224/03015 , H01L2224/03019 , H01L2224/034 , H01L2224/03622 , H01L2224/0391 , H01L2224/0401 , H01L2224/04042 , H01L2224/05 , H01L2224/05565 , H01L2224/05567 , H01L2224/05624 , H01L2224/131 , H01L2224/13147 , H01L2224/32145 , H01L2224/45124 , H01L2224/45147 , H01L2224/48227 , H01L2224/48463 , H01L2224/48507 , H01L2224/48824 , H01L2224/73265 , H01L2924/01012 , H01L2924/01029 , H01L2924/0103 , H01L2924/10253 , H01L2924/10271 , H01L2924/10329 , H01L2924/14 , H01L2924/365 , H01L2924/3651 , H01L2924/014 , H01L2924/00014 , H01L2924/00
摘要： A packaged semiconductor device is made by forming a conductive pad on an external surface of an integrated circuit device, forming a passivation layer over the conductive pad, removing a portion of the passivation layer over a bond area on the conductive pad, forming a sacrificial anode around a majority of a periphery surrounding the bond area, forming a conductive bond in the bond area, and forming an encapsulating material around the conductive bond and an exposed portion of the sacrificial anode.
摘要翻译：通过在集成电路器件的外表面上形成导电焊盘来形成封装的半导体器件，在导电焊盘上方形成钝化层，在导电焊盘上的接合区域上去除钝化层的一部分，形成牺牲阳极在围绕结合区域的周边的大部分周围，在接合区域中形成导电结合，以及在导电接合周围形成封装材料和牺牲阳极的暴露部分。

23. 发明申请

US20110261491A1 MONITOR CIRCUIT FOR DETERMINING THE LIFETIME OF A SEMICONDUCTOR DEVICE 有权
标题翻译：用于确定半导体器件寿命的监视器电路
公开(公告)号：US20110261491A1
公开(公告)日：2011-10-27
申请号：US12764689
申请日：2010-04-21
申请人： JASON C. PERKEY , Scott S. Roth , Tim J. Zoerner
发明人： JASON C. PERKEY , Scott S. Roth , Tim J. Zoerner
IPC分类号： H02H3/02 , H01L21/768
CPC分类号： G01R31/2642
摘要： A circuit comprises a first conductor, a second conductor, and a first detect and disconnect circuit. The first conductor is coupled to a first power supply voltage terminal. The second conductor is positioned a first predetermined distance from the first conductor. The first detect and disconnect circuit has a first terminal coupled to the second conductor and a second terminal coupled to a second power supply voltage terminal. The first detect and disconnect circuit detects a first electrical property change between the second conductor and the first conductor. In response to detecting the change in the first electrical property, the second conductor is disconnected from the second power supply voltage terminal. A method for manufacturing a semiconductor device comprising the circuit is also provided.
摘要翻译：电路包括第一导体，第二导体和第一检测和断开电路。第一导体耦合到第一电源电压端子。第二导体位于距第一导体第一预定距离处。第一检测和断开电路具有耦合到第二导体的第一端子和耦合到第二电源电压端子的第二端子。第一检测和断开电路检测第二导体和第一导体之间的第一电特性变化。响应于检测到第一电气特性的变化，第二导体与第二电源电压端子断开。还提供了一种制造包括该电路的半导体器件的方法。

24. 发明授权

US07741195B2 Method of stimulating die circuitry and structure therefor 有权
标题翻译：刺激电路及其结构的方法
公开(公告)号：US07741195B2
公开(公告)日：2010-06-22
申请号：US11420551
申请日：2006-05-26
申请人： Mohammed K. Rashid , Mahbub M. Rashed , Scott S. Roth
发明人： Mohammed K. Rashid , Mahbub M. Rashed , Scott S. Roth
IPC分类号： H01L21/00
CPC分类号： G01R31/2884 , G01R31/2831 , H01L22/32 , H01L2224/02166 , H01L2224/05554
摘要： A method includes providing a wafer having a first die and a scribe grid, where the first die has die circuitry and a bond pad electrically connected to the die circuitry, and where the scribe grid has a scribe grid pad electrically connected to the die circuitry. The method further includes accessing the scribe grid pad to stimulate the die circuitry. A wafer includes a first die. The first die includes die circuitry, a plurality of conductive layers, and a bond pad electrically connected to the die circuitry via at least one conductive layer of the plurality of conductive layers. The wafer includes a scribe grid having a scribe grid pad, and an interconnect electrically connecting the scribe grid pad to the die circuitry. The plurality of die of the wafer can then be singulated, and at least one of the singulated die can be packaged.
摘要翻译：一种方法包括提供具有第一管芯和划线栅格的晶片，其中第一管芯具有管芯电路和电连接到管芯电路的接合焊盘，并且其中划线栅具有电连接到管芯电路的划线栅焊盘。该方法还包括访问划线网格焊盘以刺激管芯电路。晶片包括第一模具。第一裸片包括晶片电路，多个导电层以及通过多个导电层中的至少一个导电层电连接到管芯电路的焊盘。晶片包括具有划线网格焊盘的划线网格，以及将划线网格焊盘与管芯电路电连接的互连。然后可以对晶片的多个裸片进行单片化，并且可以封装单个模具中的至少一个。

25. 发明授权

US5616941A Electrically programmable read-only memory cell 失效
标题翻译：电可编程只读存储单元
公开(公告)号：US5616941A
公开(公告)日：1997-04-01
申请号：US531357
申请日：1995-09-20
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/8247 , H01L29/423 , H01C29/788 , H01C27/148
CPC分类号： H01L27/11521 , H01L29/42324
摘要： A floating gate (51)is formed to have a cavity (52) that increases the capacitive coupling between the floating gate (51) and a control gate for the memory cell. The memory cell may be used in EPROM, EEPROM, and flash EEPROM arrays and may be programmed and erased by hot carrier injection, Fowler-Nordheim tunneling or the like. The process sequence for forming the cavity (52) of the floating gate (51) has good process margin allowing some lithographic misalignment. In one embodiment, a multi-tiered floating gate may be formed. The multi-tier structure allows the capacitive coupling to further increase without occupying more area.
摘要翻译：浮动栅极（51）形成为具有增加浮动栅极（51）和存储单元的控制栅极之间的电容耦合的空腔（52）。存储单元可以用在EPROM，EEPROM和闪存EEPROM阵列中，并且可以通过热载流子注入，Fowler-Nordheim隧道等来编程和擦除。用于形成浮动栅极（51）的空腔（52）的工艺顺序具有良好的工艺裕度，允许一些光刻未对准。在一个实施例中，可以形成多层浮动栅极。多层结构允许电容耦合进一步增加而不占用更多的面积。

26. 发明授权

US5455194A Encapsulation method for localized oxidation of silicon with trench isolation 失效
标题翻译：具有沟槽隔离的硅的局部氧化的封装方法
公开(公告)号：US5455194A
公开(公告)日：1995-10-03
申请号：US398844
申请日：1995-03-06
申请人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth
发明人： Barbara Vasquez , Michael P. Masquelier , Scott S. Roth
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76
CPC分类号： H01L21/763 , H01L21/76227 , Y10S148/05
摘要： A method for the fabrication of a trench isolation region (44) includes the deposition of first, second, and third oxidizable layers (28, 34, 42). The first oxidizable layer (28) is deposited to overlie the surface of a trench (12) formed in a semiconductor substrate (10). The first oxidizable layer (28) also fills a recess (26) formed in a masking layer (14), and resides adjacent to the upper surface of the trench (12). After oxidizing the first oxidizable layer (28), a second oxidizable layer (34) is deposited to fill the trench (12). A third oxidizable layer (42) is deposited to overlie the second oxidizable layer (34) and fills a remaining portion of the recess (26). An oxidation process is performed to oxidize oxidizable layer (42) and a portion of second oxidizable layer (34) to form a trench isolation region (44). In an alternative embodiment of the invention, a shallow isolation region (46) is formed in proximity to the trench isolation region ( 44).
摘要翻译：用于制造沟槽隔离区（44）的方法包括沉积第一，第二和第三可氧化层（28,34,42）。沉积第一可氧化层（28）以覆盖形成在半导体衬底（10）中的沟槽（12）的表面。第一可氧化层（28）还填充形成在掩模层（14）中的凹部（26），并且邻近沟槽（12）的上表面驻留。在氧化第一可氧化层（28）之后，沉积第二可氧化层（34）以填充沟槽（12）。沉积第三可氧化层（42）以覆盖第二可氧化层（34）并填充凹部（26）的剩余部分。进行氧化处理以氧化可氧化层（42）和一部分第二可氧化层（34）以形成沟槽隔离区（44）。在本发明的替代实施例中，在隔离区（44）附近形成浅隔离区（46）。

27. 发明授权

US5374573A Method of forming a self-aligned thin film transistor 失效
标题翻译：形成自对准薄膜晶体管的方法
公开(公告)号：US5374573A
公开(公告)日：1994-12-20
申请号：US200591
申请日：1994-02-23
申请人： Kent J. Cooper , Scott S. Roth , James D. Hayden , Howard C. Kirsch
发明人： Kent J. Cooper , Scott S. Roth , James D. Hayden , Howard C. Kirsch
IPC分类号： H01L29/78 , H01L21/336 , H01L27/11 , H01L29/417 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L27/1108 , H01L29/41733 , H01L29/66757
摘要： A thin film transistor with self-aligned source and drain regions is fabricated, in one embodiment, by forming an opening (124) in a dielectric layer (118) which overlies a substrate (116). A semiconductive sidewall spacer (130) is formed around the perimeter (126) of the opening (124) and adjacent to the sidewall (128) of the opening (124). A first electrode region (120) is electrically coupled to a first portion of the semiconductive sidewall spacer (130) at a first location along the perimeter (126) of the opening (124) which lies only in the second lateral half of the opening (124). A second electrode region (122) is electrically coupled to a second portion of the semiconductive sidewall spacer (130) at a second location along the perimeter (126) of the opening (124) which lies only in the first lateral half of the opening (124). A dielectric layer (132) is formed adjacent to the semiconductive sidewall spacer (130). A control electrode (134) is formed adjacent to the dielectric layer (132).
摘要翻译：在一个实施例中，通过在覆盖在基板（116）上的电介质层（118）中形成开口（124）来制造具有自对准源区和漏区的薄膜晶体管。围绕开口（124）的周边（126）并且邻近开口（124）的侧壁（128）形成半导体侧壁间隔物（130）。第一电极区域（120）在位于开口（124）的仅位于开口的第二侧面半部分（124）的周边（126）的第一位置处电耦合到半导体侧壁间隔件（130）的第一部分 124）。第二电极区域（122）在位于开口（124）的仅位于开口的第一侧面半部分（124）的周边（126）的第二位置处电连接到半导体侧壁间隔物（130）的第二部分 124）。邻近半导体侧壁间隔物（130）形成介电层（132）。与电介质层（132）相邻地形成控制电极（134）。

28. 发明授权

US5374572A Method of forming a transistor having an offset channel section 失效
标题翻译：一种形成具有偏移通道部分的晶体管的方法
公开(公告)号：US5374572A
公开(公告)日：1994-12-20
申请号：US95502
申请日：1993-07-22
申请人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
发明人： Scott S. Roth , William C. McFadden , Alexander J. Pepe
IPC分类号： H01L21/8244 , H01L27/11 , H01L29/45 , H01L29/786 , H01L21/265
CPC分类号： H01L29/78696 , H01L27/11 , H01L27/1108 , H01L29/458 , H01L29/78624 , Y10S148/15
摘要： The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.
摘要翻译：本发明包括具有第一和第二部分的沟道区的晶体管，其中所述部分具有大致垂直于彼此的长度。防止发明还包括SRAM单元中的晶体管和用于形成晶体管和SRAM单元的处理。在所描述的实施例中，第一部分具有大致垂直的长度，并且第二部分具有通常沿横向方向延伸的长度。第一部分可以是硅插头的未掺杂或轻掺杂的部分。插塞可以形成包括蚀刻或抛光步骤。

29. 发明授权

US5286674A Method for forming a via structure and semiconductor device having the same 失效
标题翻译：用于形成通孔结构的方法和具有该通孔结构的半导体器件
公开(公告)号：US5286674A
公开(公告)日：1994-02-15
申请号：US844044
申请日：1992-03-02
申请人： Scott S. Roth , Howard C. Kirsch
发明人： Scott S. Roth , Howard C. Kirsch
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76802 , Y10S438/97
摘要： A semiconductor device (20) makes contact between a first metal line (22) and an overlying second metal line (24) without the need for a conductive landing pad. Sidewall spacers (30) are formed adjacent sides of metal lines (22) such that during formation of a via (34) in an overlying dielectric layer (32), the sidewall spacer prevent trenching of underlying dielectric layer (28) if the via is misaligned. The sidewall spacers are formed of a dielectric material which has an etch rate which is significantly slower than the etch rate of dielectric layer (32). In another embodiment, portions of the sidewall spacers are selectively removed prior to depositing a second metal layer (42). Upon depositing the second metal layer, the side of metal line (22) is locally clad with the second metal to increase contact area and lowering contact resistance.
摘要翻译：半导体器件（20）在第一金属线（22）和上覆的第二金属线（24）之间接触，而不需要导电的着陆焊盘。在金属线（22）的相邻侧面处形成侧壁间隔件（30），使得在形成覆盖介质层（32）中的通路（34）时，侧壁间隔物防止下面的介电层（28）的沟槽，如果通孔是不对齐侧壁间隔物由电介质材料形成，该电介质材料具有比介电层（32）的蚀刻速率显着更慢的蚀刻速率。在另一个实施例中，在沉积第二金属层（42）之前选择性地去除侧壁间隔物的部分。在沉积第二金属层时，金属线（22）的一侧用第二金属局部包覆以增加接触面积并降低接触电阻。

30. 发明授权

US5158687A Methods of removing undesired ions from aqueous solutions 失效
标题翻译：从水溶液中除去不需要的离子的方法
公开(公告)号：US5158687A
公开(公告)日：1992-10-27
申请号：US728490
申请日：1991-07-11
申请人： Charles L. Terry , Leo F. Bohanon , Scott S. Roth
发明人： Charles L. Terry , Leo F. Bohanon , Scott S. Roth
IPC分类号： C02F1/52 , C02F1/70
CPC分类号： C02F1/70 , C02F1/5236 , Y10S204/13 , Y10S210/904 , Y10S210/913
摘要： A method of removing undesired ions, such as chlorine, hypochlorite, chromium, cyanide and heavy metal ions, from an aqueous preparation containing one or more of said ions consists of adding to the aqueous preparation an effective amount of magnesium bisulfite to inactivate the undesired ions and then adjusting the pH of the mixture to an appropriate pH. Compositions containing magnesium bisulfite and divalent and trivalent ions are disclosed.
摘要翻译：从含有一种或多种所述离子的含水制剂中除去不需要的离子如氯，次氯酸盐，铬，氰化物和重金属离子的方法包括向水性制剂中加入有效量的亚硫酸氢镁以使不希望的离子失活然后将混合物的pH调节到合适的pH。公开了含有亚硫酸氢镁和二价和三价离子的组合物。

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