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21. 发明申请

US20160093549A1 INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT 有权
标题翻译：用于集成电路集成电路材料和芯片引线的集成电路加热器，并优化集成电路器件的性能
公开(公告)号：US20160093549A1
公开(公告)日：2016-03-31
申请号：US14496870
申请日：2014-09-25
申请人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
发明人： Douglas M. Reber , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L23/34
CPC分类号： H01L25/065 , G01K7/00 , G01K7/427 , H01L2924/0002 , H01L2924/00
摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.
摘要翻译：一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

22. 发明授权

US09064785B2 Electronic device including a capacitor and a process of forming the same 有权
标题翻译：包括电容器的电子器件及其形成方法
公开(公告)号：US09064785B2
公开(公告)日：2015-06-23
申请号：US11780900
申请日：2007-07-20
申请人： Bradley P. Smith , Edward O. Travis
发明人： Bradley P. Smith , Edward O. Travis
IPC分类号： G02F1/1333 , G02F1/1343 , H01L21/66 , H01L49/02
CPC分类号： H01L22/20 , H01L22/12 , H01L28/40
摘要： An electronic device can include electronic components and an insulating layer overlying the electronic components. The electronic device can also include a capacitor overlying the insulating layer, wherein the capacitor includes a first electrode and a second electrode. The second electrode can include an opening, wherein from a top view, a defect lies within the opening. In another aspect, a process of forming an electronic device can include forming a first capacitor electrode layer over a substrate, forming a dielectric layer over the first capacitor electrode layer, and forming a second capacitor electrode layer over the dielectric layer. The process can also include detecting a defect and removing a first portion of the second capacitor electrode layer corresponding to the defect, wherein a second portion of the second capacitor electrode layer remains over the dielectric layer.
摘要翻译：电子设备可以包括电子部件和覆盖电子部件的绝缘层。电子器件还可以包括覆盖绝缘层的电容器，其中电容器包括第一电极和第二电极。第二电极可以包括开口，其中从顶部看，缺陷位于开口内。另一方面，形成电子器件的方法可以包括在衬底上形成第一电容器电极层，在第一电容器电极层上形成电介质层，并在电介质层上形成第二电容器电极层。该过程还可以包括检测缺陷并去除对应于缺陷的第二电容器电极层的第一部分，其中第二电容器电极层的第二部分保留在电介质层上。

23. 发明授权

US09032615B2 Method for forming an electrical connection between metal layers 有权
标题翻译：在金属层之间形成电连接的方法
公开(公告)号：US09032615B2
公开(公告)日：2015-05-19
申请号：US13562534
申请日：2012-07-31
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01K3/10 , G06F17/50 , H01L21/768 , H01L23/522 , H01L29/41
CPC分类号： H01L21/76816 , G06F17/5077 , H01L23/5226 , H01L29/41 , H01L2924/0002 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.
摘要翻译：一种方法形成第一金属层和第二金属层之间的电连接。第二金属层在第一金属层之上。在第一金属层和第二金属层之间形成第一通孔。获得预计达到第一个通道的空缺数量的首要措施。如果空位的测量超过第一预定数量，则形成第一金属层和第二金属层中的至少一个的第二通孔。

24. 发明申请

US20140038317A1 METHOD FOR FORMING AN ELECTRICAL CONNECTION BETWEEN METAL LAYERS 有权
标题翻译：在金属层之间形成电气连接的方法
公开(公告)号：US20140038317A1
公开(公告)日：2014-02-06
申请号：US13562534
申请日：2012-07-31
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , G06F17/5077 , H01L23/5226 , H01L29/41 , H01L2924/0002 , Y10T29/49124 , Y10T29/49155 , Y10T29/49165 , H01L2924/00
摘要： A method forms an electrical connection between a first metal layer and a second metal layer. The second metal layer is above the first metal layer. A first via is formed between the first metal layer and the second metal layer. A first measure of a number of vacancies expected to reach the first via is obtained. A second via in at least one of the first metal layer and the second metal layer is formed if the measure of vacancies exceeds a first predetermined number.
摘要翻译：一种方法形成第一金属层和第二金属层之间的电连接。第二金属层在第一金属层之上。在第一金属层和第二金属层之间形成第一通孔。获得预计达到第一个通道的空缺数量的首要措施。如果空位的测量超过第一预定数量，则形成第一金属层和第二金属层中的至少一个的第二通孔。

25. 发明授权

US08581390B2 Semiconductor device with heat dissipation 有权
标题翻译：半导体器件散热
公开(公告)号：US08581390B2
公开(公告)日：2013-11-12
申请号：US13442015
申请日：2012-04-09
申请人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
发明人： Edward O. Travis , Douglas M. Reber , Mehul D. Shroff
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H01L23/3677 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/29 , H01L24/30 , H01L24/32 , H01L24/73 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/0657 , H01L2224/13082 , H01L2224/131 , H01L2224/13147 , H01L2224/14164 , H01L2224/16225 , H01L2224/16227 , H01L2224/29015 , H01L2224/29082 , H01L2224/291 , H01L2224/29147 , H01L2224/30154 , H01L2224/30164 , H01L2224/30177 , H01L2224/73103 , H01L2224/73203 , H01L2224/81801 , H01L2224/83801 , H01L2224/9211 , H01L2225/06513 , H01L2225/06589 , H01L2924/00012 , H01L2924/00014 , H01L2924/014 , H01L2224/81 , H01L2224/83
摘要： A semiconductor assembly includes a semiconductor device and a connecting structure. The semiconductor device includes an interconnect region over a semiconductor substrate and a pillar layer having a plurality of pillar contacts on the interconnect region. The pillar layer also includes a plurality of radial heat conductors that have at least a portion overlying a heat source that is within and overlies the semiconductor substrate. Each radial heat conductor extends a length radially from the heat source that is at least twice as great as the diameter of the pillars. The connecting structure includes a connecting substrate that supports a first corresponding pillar contact that is in contact with a first pillar contact of the plurality of pillar contacts. The first connecting structure further includes a heat conductor, supported by the substrate, in contact with a first radial heat conductor of the plurality of radial heat conductors.
摘要翻译：半导体组件包括半导体器件和连接结构。半导体器件包括半导体衬底上的互连区域和在互连区域上具有多个柱状触点的柱层。柱层还包括多个径向热导体，其具有覆盖在半导体衬底内并覆盖半导体衬底的热源的至少一部分。每个径向导热体从热源的径向延伸至少两倍于柱的直径。连接结构包括支撑与多个柱接触件的第一柱接触件接触的第一对应的柱接触件的连接基板。所述第一连接结构还包括由所述基板支撑的与所述多个径向导热体的第一径向导热体接触的导热体。

26. 发明授权

US07622339B2 EPI T-gate structure for CoSi2 extendibility 有权
标题翻译： EPI T-gate结构，CoSi2可扩展性
公开(公告)号：US07622339B2
公开(公告)日：2009-11-24
申请号：US11340049
申请日：2006-01-26
申请人： Mark D. Hall , Dharmesh Jawarani , Mehul D. Shroff , Edward O. Travis
发明人： Mark D. Hall , Dharmesh Jawarani , Mehul D. Shroff , Edward O. Travis
IPC分类号： H01L21/338
CPC分类号： H01L21/28114 , H01L29/42376 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.
摘要翻译：半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的顶部临界尺寸（例如，在40nm以上），使得硅化物可以在至少T形结构（96）的上部区域（90）中由第一材料（例如CoSi 2）形成，而不会增加在较小的临界尺寸下，某些硅化物可能会发生聚集和排空引起的电阻。

27. 发明授权

US06764919B2 Method for providing a dummy feature and structure thereof 有权
标题翻译：提供虚拟特征及其结构的方法
公开(公告)号：US06764919B2
公开(公告)日：2004-07-20
申请号：US10327498
申请日：2002-12-20
申请人： Kathleen C. Yu , Edward O. Travis , Bradley P. Smith
发明人： Kathleen C. Yu , Edward O. Travis , Bradley P. Smith
IPC分类号： H01L2176
CPC分类号： H01L21/76852 , H01L21/7682 , H01L21/76874 , H01L23/522 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Dummy features (64, 65a, 65b, 48a, 48b) are formed within an interlevel dielectric layer (36). A non-gap filling dielectric layer (72) is formed over the dummy features (64, 65a, 65b, 48a, 48b) to form voids (74) between dummy features (64, 65a, 65b, 48a, 48b) or between a dummy feature (48a) and a current carrying region (44). The dummy features (64, 65a, 65b, 48a, 48b) can be conductive (48a, 48b) and therefore, formed when forming the current carrying region (44). In another embodiment, the dummy features (64, 65a, 65b, 48a, 48b) are insulating (64, 65a, 65b) and are formed after forming the current carrying region (44). In yet another embodiment, both conductive and insulating dummy features (64, 65a, 65b, 48a, 48b) are formed. In a preferred embodiment, the voids (74) are air gaps, which are a low dielectric constant material.
摘要翻译：在层间电介质层（36）内形成虚拟特征（64,65a，65b，48a，48b）。在虚拟特征（64,65a，65b，48a，48b）上形成无间隙填充介电层（72），以在虚拟特征（64,65a，65b，48a，48b）之间或之间形成空隙（74）虚拟特征（48a）和载流区（44）。虚拟特征（64,65a，65b，48a，48b）可以是导电的（48a，48b），因此在形成载流区域（44）时形成。在另一个实施例中，虚拟特征（64,65a，65b，48a，48b）是绝缘的（64,65a，65b），并且在形成载流区域（44）之后形成。在又一个实施例中，形成导电和绝缘虚拟特征（64,65a，65b，48a，48b）。在优选实施例中，空隙（74）是作为低介电常数材料的气隙。

28. 发明授权

US06614062B2 Semiconductor tiling structure and method of formation 失效
公开(公告)号：US06614062B2
公开(公告)日：2003-09-02
申请号：US09761885
申请日：2001-01-17
申请人： Sejal N. Chheda , Edward O. Travis
发明人： Sejal N. Chheda , Edward O. Travis
IPC分类号： H10L2710
CPC分类号： H01L21/76229
摘要： A semiconductor device and method of fabrication are disclosed. The device includes a first trench isolation region having an allowable tiling area and a second trench isolation region having an allowable tiling area, wherein the second trench isolation region is doped differently from the first trench isolation region. First tile structures disposed within first trench isolation region have a first set of design parameters while second tile structures disposed within the second trench isolation region have a second set of design parameters. At least one of the first set of design parameters is different from a corresponding design parameter in the second set of design parameters. The corresponding design parameters may include the density, size, pitch, shape, exclusion distance, minimum width, minimum length, and minimum area. The first trench isolation region may be doped with a first-type dopant and the second trench isolation region may be undoped or doped with an opposite second-type dopant.

29. 发明授权

US06613688B1 Semiconductor device and process for generating an etch pattern 有权
标题翻译：用于产生蚀刻图案的半导体器件和工艺
公开(公告)号：US06613688B1
公开(公告)日：2003-09-02
申请号：US10133061
申请日：2002-04-26
申请人： Thomas M. Brown , Edward O. Travis , Jeffrey C. Haines
发明人： Thomas M. Brown , Edward O. Travis , Jeffrey C. Haines
IPC分类号： H01L21302
CPC分类号： H01L21/31055 , H01L21/31053
摘要： A model-based approach for generating an etch pattern to decrease topographical uniformity involves placing reverse dummy features (50, 52, 70) in a region of a semiconductor substrate (40, 60) according to the topography of the region and adjacent regions. The reverse dummy features are placed inconsistently over the semiconductor substrate (40, 60) because the need for reverse dummy features is inconsistent and varies from design to design. In one embodiment, the reverse dummy features (50, 52, 70) having varying widths are placed with varying spacing between them and are placed in different regions. The determination of location, size and spacing of the reverse dummy features (50, 52, 70) is determined based upon the uniformity effect over the entire semiconductor die and may be used in conjunction with the placement of printed dummy features. After placing the reverse dummy features (50, 52, 70), a planarization process may be performed to remove the reverse dummy features, which improves the planarization.
摘要翻译：用于产生减少形貌均匀性的蚀刻图案的基于模型的方法包括根据该区域和相邻区域的形貌将反虚拟特征（50,52,70）放置在半导体衬底（40,60）的区域中。反向虚拟特征被放置在半导体衬底（40,60）上不一致，因为对于反向虚拟特征的需要是不一致的，并且从设计到设计都是不同的。在一个实施例中，具有变化的宽度的反向虚拟特征（50,52,70）以它们之间的间隔变化地放置并且被放置在不同的区域中。基于在整个半导体管芯上的均匀性效应来确定反向虚拟特征（50,52,70）的位置，尺寸和间距的确定，并且可以与打印的伪特征的放置一起使用。在放置反向虚拟特征（50,52,70）之后，可以执行平坦化处理以去除反向虚拟特征，这改善了平坦化。

30. 发明授权

US09443804B2 Capping layer interface interruption for stress migration mitigation 有权
标题翻译：封盖层接口中断，用于减轻压力迁移
公开(公告)号：US09443804B2
公开(公告)日：2016-09-13
申请号：US13956068
申请日：2013-07-31
申请人： Mehul D. Shroff , Douglas M. Reber , Edward O. Travis
发明人： Mehul D. Shroff , Douglas M. Reber , Edward O. Travis
IPC分类号： H01L23/48 , H01L23/532 , H01L21/768
CPC分类号： H01L23/53238 , H01L21/768 , H01L21/76846 , H01L21/76849 , H01L23/528 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.
摘要翻译：半导体器件包括衬底，由衬底支撑的电介质层，与电介质层相邻的互连，所述互连包括传导材料和沿导电材料和电介质层之间的互连侧壁设置的阻挡材料，以及层布置在互连上以建立导电材料，阻挡材料和层之间的界面。沿着互连的一部分布置板以中断接口。

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