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21. 发明授权

US06911733B2 Semiconductor device and electronic device 失效
标题翻译：半导体器件和电子器件
公开(公告)号：US06911733B2
公开(公告)日：2005-06-28
申请号：US10372898
申请日：2003-02-26
申请人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
发明人： Hiroshi Kikuchi , Norio Nakazato , Hideko Ando , Takashi Suga , Satoru Isomura , Takashi Kubo , Hiroyasu Sasaki , Masanori Fukuhara , Naotaka Tanaka , Fujiaki Nose
IPC分类号： H01L23/66 , H05K1/02 , H05K3/36 , H01L23/34
CPC分类号： H05K1/0243 , H01L23/66 , H01L2223/6616 , H01L2223/6627 , H01L2224/16 , H01L2224/16225 , H01L2224/32188 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2924/01079 , H01L2924/09701 , H01L2924/15173 , H01L2924/15174 , H01L2924/15192 , H01L2924/15311 , H01L2924/16152 , H01L2924/1903 , H01L2924/19106 , H01L2924/3011 , H01L2924/3025 , H05K1/0219 , H05K3/361 , H05K2201/10522 , H05K2201/1053 , H05K2201/10659 , H05K2201/10681 , H05K2201/10734 , H01L2924/00014 , H01L2924/00
摘要： A high-frequency signal from a tape-shaped line section having a surface layer signal lead and surface layer GND lead disposed on both sides thereof is directly inputted to a semiconductor chip via a signal surface layer wiring of a package substrate and through solder bump electrodes. Alternatively, a high-frequency signal from the semiconductor chip is outputted to the outside via the tape-shaped line section in reverse. Owing to the transmission of the high-frequency signal by only a microstrip line at the whole surface layer of the package substrate, the high-frequency signal can be transmitted by only the microstrip line at the surface layer without through vias or the like. Accordingly, the high-frequency signal can be transmitted without a loss in frequency characteristic, and a high-quality high-frequency signal can be transmitted with a reduction in loss at high-frequency transmission.
摘要翻译：来自具有布置在其两侧的表面层信号引线和表面层GND引线的带状线段的高频信号经由封装衬底的信号表面层布线直接输入到半导体芯片，并通过焊料凸块电极。或者，来自半导体芯片的高频信号经由带状线路部分反向输出到外部。由于仅在封装衬底的整个表面层处的微带线传输高频信号，所以高频信号可以仅通过表层的微带线传输，而不需要通过通孔等。因此，可以不损失频率特性来发送高频信号，并且可以在高频率传输时以低损耗的方式发送高质量的高频信号。

22. 发明授权

US06530066B1 Method of computing wiring capacitance, method of computing signal propagation delay due to cross talk and computer-readable recording medium storing such computed data 有权
标题翻译：计算布线电容的方法，计算由串扰引起的信号传播延迟的方法以及存储这种计算数据的计算机可读记录介质
公开(公告)号：US06530066B1
公开(公告)日：2003-03-04
申请号：US09666863
申请日：2000-09-21
申请人： Yuko Ito , Satoru Isomura
发明人： Yuko Ito , Satoru Isomura
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： The present invention is to provide a method of computing wiring capacitance to be able to get parasitic capacity depending on the wiring at high speed and with great accuracy, and to provide a method of computing signal propagation delay due to cross talk to be able to remove surplus margins at high speed when delay is predicted. In design of LSIs such as microprocessors or the like, total capacity Ctotal per unit length is determined about each of a plurality of models altering adjacent wiring ((a) no adjacent wiring, (b) one-side adjacent wiring, and (c) both-sides adjacent wiring) and/or crossing ratios ((i) 0%, (ii) 33%, (iii) 67%, and (iv) 100%) and, thereby, a library is formed from these to design the LSI. Regarding characteristic of this total capacity per unit length, the capacity depending on increase of the crossing ratio has a high increase rate in an area of a low crossing ratio, while the capacity depending on increase of the crossing ratio has the low increase rate in high crossing ratio. Regarding a case of no adjacent wiring, the capacity depending on increase of crossing ratio has a high increase rate in comparison to a case of one-side or both-sides adjacent wiring.
摘要翻译：本发明提供一种计算布线电容的方法，其能够根据高速和高精度的布线获得寄生电容，并且提供一种计算由串扰引起的信号传播延迟的方法，以能够去除延迟预测时高速的剩余利润。在诸如微处理器等的LSI的设计中，关于改变相邻布线（（a）没有相邻布线，（b）单面相邻布线）的多个模型中的每一个模型确定每单位长度的总容量Ctotal，（c）两侧相邻布线）和/或交叉比（（i）0％，（ii）33％，（iii）67％和（iv）100％），由此形成文库以设计 LSI。关于该单位长度的总容量的特性，与交叉比的增加相关的容量在低交叉比的面积上具有高的增加率，而根据交叉比的增加的容量具有较高的增加率交叉比。关于没有相邻布线的情况，与一侧或两侧相邻布线的情况相比，与交叉比的增加相关的容量具有高的增加率。

23. 发明授权

US06359472B2 Semiconductor integrated circuit and its fabrication method 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US06359472B2
公开(公告)日：2002-03-19
申请号：US09791831
申请日：2001-02-26
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L2704
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： An integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which p-channel transistor Tp of the CMOS circuit is set, with a supply line Vdd through switching transistor Tps, and electrically connecting a p-type well 3, in which n-channel transistor Tn of the CMOS circuit is set, with supply line Vss through switching transistor Tns. Thermal runaway due to leakage current can be controlled by turning off switching transistors Tps and Tns and supplying potentials suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the integrated circuit is being tested. Fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the voltages Vdd and Vss, respectively.
摘要翻译：具有CMOS电路的集成电路，其通过将n型阱2（其中CMOS电路的p沟道晶体管Tp被置位）与通过开关晶体管Tps的电源线Vdd电连接而构成，并且电连接p型阱如图3所示，其中CMOS电路的n沟道晶体管Tn被设置，电源线Vss通过开关晶体管Tns。当集成电路被测试时，可以通过关断开关晶体管Tps和Tns并从外部单元向n型阱2和p型阱3提供适合于测试的电位来控制由于泄漏电流引起的热失控。通过接通开关晶体管Tps和Tns并分别将n型阱2和p型阱3分别设置为电压Vdd和Vss可以防止闩锁现象和操作速度的波动。

24. 发明授权

US06194915B1 Semiconductor integrated circuit device and process for manufacturing the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06194915B1
公开(公告)日：2001-02-27
申请号：US09077829
申请日：1998-06-04
申请人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
发明人： Michiaki Nakayama , Masato Hamamoto , Kazutaka Mori , Satoru Isomura
IPC分类号： H01L2704
CPC分类号： H01L27/1104 , H01L27/0921 , H01L27/0928
摘要： To provide a semiconductor integrated circuit having a CMOS circuit constituted by electrically connecting an n-type well 2, in which one transistor Tp for constituting the CMOS circuit is set, with a first power-supply-voltage line Vdd through a switching transistor Tps, and electrically connecting a p-type well 3 in which the other transistor Tn for constituting the CMOS circuit is set with a second power-supply-voltage line Vss through a switching transistor Tns. Moreover, the semiconductor integrated circuit is constituted so that thermal runaway due to leakage current can be controlled by turning off the switching transistors Tps and Tns and supplying a potential suitable for a test to the n-type well 2 and the p-type well 3 from an external unit when the semiconductor integrated circuit is being tested. Furthermore, the semiconductor integrated circuit is constituted so that fluctuations of the latch-up phenomenon and operation speed can be prevented by turning on the switching transistors Tps and Tns and setting the n-type well 2 and the p-type well 3 to the power supply voltages Vdd and Vss, respectively.
摘要翻译：为了提供具有CMOS电路的半导体集成电路，该CMOS电路通过电连接构成CMOS电路的一个晶体管Tp与通过开关晶体管Tps的第一电源电压线Vdd电连接的n型阱2，并且通过开关晶体管Tns将构成CMOS电路的另一个晶体管Tn与p型阱3电连接到第二电源电压线Vss。此外，半导体集成电路被构造成使得可以通过关断开关晶体管Tps和Tns并且向n型阱2和p型阱3提供适合于测试的电位来控制由漏电流引起的热失控当半导体集成电路被测试时，从外部单元。此外，半导体集成电路构成为通过接通开关晶体管Tps和Tns并将n型阱2和p型阱3设置为功率来防止闩锁现象和操作速度的波动电源电压Vdd和Vss。

25. 发明授权

US5306948A Semiconductor device and semiconductor module having auxiliary high power supplying terminals 失效
标题翻译：具有辅助高功率供电端子的半导体器件和半导体模块
公开(公告)号：US5306948A
公开(公告)日：1994-04-26
申请号：US950332
申请日：1992-09-24
申请人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
发明人： Takeo Yamada , Satoru Isomura , Atsushi Shimizu , Yuko Ito , Tohru Kobayashi , Mikinori Kawaji
IPC分类号： H01L21/66 , G01R1/04 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/498 , H01L25/065 , H01L23/02 , H01L23/12
CPC分类号： H01L25/0655 , G01R1/0483 , H01L23/053 , H01L23/057 , H01L23/473 , H01L23/49805 , H01L2224/16 , H01L2224/16225 , H01L2224/73253 , H01L2924/01014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152
摘要： Herein disclosed is a chip-carrier type semiconductor device adopting the MCC structure, in which a semiconductor pellet is mounted on the surface of the base substrate and in which mounting terminals to be connected with external terminals of the semiconductor pellet are mounted on the rear surface of the base substrate. In order to effect a test such as screening easily and inexpensively even if the mounting terminals are multiplied or miniaturized, the chip-carrier type semiconductor device adopting the MCC structure is equipped on the side surfaces of the base substrate with auxiliary terminals to be electrically connected with a plurality of external terminals which are arrayed on an element formed main surface of the semiconductor pellet.
摘要翻译：这里公开的是采用MCC结构的芯片载体型半导体器件，其中半导体芯片安装在基底表面上，并且其中与半导体芯片的外部端子连接的安装端子安装在后表面的基底。即使安装端子倍增或小型化，为了实现轻松便宜地进行测试，采用MCC结构的芯片载体型半导体器件配置在具有辅助端子的基底基板的电连接多个外部端子排列在半导体芯片的形成元件的主表面上。

26. 发明授权

US4831094A Articles having shape recovering properties and a method for using it 失效
标题翻译：具有形状恢复性的制品及其使用方法
公开(公告)号：US4831094A
公开(公告)日：1989-05-16
申请号：US117924
申请日：1987-11-03
申请人： Claude Stein , Hitoshi Nagai , Akio Ueda , Satoru Isomura
发明人： Claude Stein , Hitoshi Nagai , Akio Ueda , Satoru Isomura
IPC分类号： B29C35/04 , B29C61/00 , C08L65/00
CPC分类号： C08L65/00 , B29C61/003 , B29C35/049 , B29K2023/00 , B29K2025/00 , B29K2033/04 , B29K2086/00
摘要： Articles having shape recovering properties and methods of using them are disclosed. An article is formed from a composition containing a norbornene polymer by forming said polymer into an article having a first shape, then deforming the article in the solid state to a second shape and cooling the article to a first temperature at or below the glass transition temperature of the polymer to retain said second shape, and finally heating said article to a temperature above the first temperature to recover the first shape.
摘要翻译：公开了具有形状恢复性能的制品及其使用方法。通过将所述聚合物形成具有第一形状的制品，然后使固体状态的制品变形为第二形状并将制品冷却至玻璃化转变温度或低于玻璃化转变温度的第一温度，由含有降冰片烯聚合物的组合物形成制品的聚合物以保持所述第二形状，并且最后将所述制品加热到高于第一温度的温度以回收第一形状。

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