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21. 发明申请

US20110233561A1 SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：半导体基板
公开(公告)号：US20110233561A1
公开(公告)日：2011-09-29
申请号：US13073385
申请日：2011-03-28
申请人： Taro NISHIGUCHI , Makoto Sasaki , Shin Harada , Kyoko Okita , Hiroki Inoue , Yasuo Namikawa
发明人： Taro NISHIGUCHI , Makoto Sasaki , Shin Harada , Kyoko Okita , Hiroki Inoue , Yasuo Namikawa
IPC分类号： H01L29/161
CPC分类号： H01L29/7802 , H01L21/0445 , H01L21/0475 , H01L21/2007 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/417 , H01L29/6606 , H01L29/66068
摘要： A supporting portion is made of silicon carbide. At least one layer has first and second surfaces. The first surface is supported by the supporting portion. The at least one layer has first and second regions. The first region is made of silicon carbide of a single-crystal structure. The second region is made of graphite. The second surface has a surface formed by the first region. The first surface has a surface formed by the first region, and a surface formed by the second region. In this way, a semiconductor substrate can be provided which has a region made of silicon carbide having a single-crystal structure and a supporting portion made of silicon carbide and allows for reduced electric resistance of an interface therebetween.
摘要翻译：支撑部分由碳化硅制成。至少一层具有第一和第二表面。第一表面由支撑部分支撑。所述至少一层具有第一和第二区域。第一区域由单晶结构的碳化硅制成。第二区域由石墨制成。第二表面具有由第一区域形成的表面。第一表面具有由第一区域形成的表面和由第二区域形成的表面。以这种方式，可以提供具有由具有单晶结构的碳化硅制成的区域和由碳化硅制成的支撑部分的区域并且允许其之间的界面的电阻降低的半导体衬底。

22. 发明授权

US06881658B2 Process of and apparatus for heat-treating II-VI compound semiconductors and semiconductor heat-treated by the process 失效
标题翻译：用于热处理II-VI化合物半导体的工艺和设备，以及通过该工艺热处理的半导体
公开(公告)号：US06881658B2
公开(公告)日：2005-04-19
申请号：US10243198
申请日：2002-09-13
申请人： Yasuo Namikawa
发明人： Yasuo Namikawa
IPC分类号： H01L29/221 , C30B31/10 , C30B33/00 , H01L21/22 , H01L21/225 , H01L21/324 , H01L21/385 , H01L21/477 , H01L33/28 , H01L21/28
CPC分类号： H01L21/385 , C30B29/48 , C30B33/00 , H01L33/0095 , H01L33/28
摘要： A process of heat-treating II-VI compound semiconductors reduces the electrical resistivity without the decrease in crystallinity resulting from the increase in dislocation density. The process comprises the following steps:(a) placing at least one II-VI compound semiconductor in contact with aluminum in a heat-treating chamber having the inside surface formed by at least one material selected from the group consisting of pyrolytic born nitride, hexagonal-system boron nitride, sapphire, alumina, aluminum nitride, and polycrystalline diamond; and (b) heat-treating the II-VI compound semiconductor or semiconductors in a gaseous atmosphere containing the group II element constituting part of the II-VI compound semiconductor or semiconductors. A II-VI compound semiconductor is heat-treated by the foregoing process. An apparatus for heat-treating II-VI compound semiconductors comprises components for performing the foregoing process.
摘要翻译：一种热处理II-VI化合物半导体的方法降低了电阻率，而不会由于位错密度的增加而导致结晶度的降低。该方法包括以下步骤：（a）将至少一种与铝接触的II-VI化合物半导体放置在热处理室中，所述热处理室具有由至少一种选自热解出的氮化物，六方晶系的材料形成的内表面系统氮化硼，蓝宝石，氧化铝，氮化铝和多晶金刚石; 和（b）在构成II-VI族化合物半导体或半导体的一部分的II族元素的气氛气氛中热处理II-VI族化合物半导体或半导体。通过上述方法对II-VI化合物半导体进行热处理。用于热处理II-VI化合物半导体的装置包括用于执行上述方法的组分。

23. 发明授权

US5846323A Crystal manufacturing apparatus 失效
标题翻译：水晶制造装置
公开(公告)号：US5846323A
公开(公告)日：1998-12-08
申请号：US725939
申请日：1996-10-08
申请人： Masahiro Egami , Yuh Shiohara , Yasuo Namikawa
发明人： Masahiro Egami , Yuh Shiohara , Yasuo Namikawa
IPC分类号： C30B15/00 , C30B15/26 , C30B29/22 , C30B35/00
CPC分类号： C30B29/22 , C30B15/26 , Y10T117/1032 , Y10T117/1068 , Y10T117/1088
摘要： A crystal pulling apparatus is designed to generate a thermal gradient across the melt surface to prevent nucleation of stray crystals and production of floating debris to produce a high quality crystal, and has special provisions for observing the growth behavior and crystal dimension measurements. The apparatus includes a cylindrical chamber, a crucible disposed centrally within the chamber, a cylindrical heater surrounding the crucible, an insulation member disposed on the top section of the crucible, a first transparent plate and a second transparent plate for closing the center hole in the insulation member, a pull rod passing through the center hole of the transparent plates, a crystal illumination mechanism, a crystal size determination mechanism and an ambient atmosphere flowing mechanism. The crystal size determination mechanism is provided with a quartz prism, an infrared transmitting filter on a side wall of the chamber, a revolution count circuit, phase angle setting circuit, a CCD camera, an image processing section, and a crystal size determination device having a TV monitor.
摘要翻译：设计了一种晶体拉制装置，以在熔体表面上产生热梯度，以防止杂散晶体的成核和浮选碎屑的产生，产生高质量的晶体，并且具有观察生长行为和晶体尺寸测量的特殊规定。该装置包括圆柱形腔室，设置在腔室中心的坩埚，围绕坩埚的圆柱形加热器，设置在坩埚顶部的绝缘构件，第一透明板和第二透明板，用于封闭坩埚中的中心孔绝缘构件，穿过透明板的中心孔的拉杆，晶体照明机构，晶体尺寸确定机构和环境大气流动机构。晶体尺寸确定机构设置有石英棱镜，在室的侧壁上的红外透射滤光器，转数计算电路，相位角设置电路，CCD照相机，图像处理部分和晶体尺寸确定装置，其具有电视监视器。

24. 发明授权

US5707441A Method for preparing an oxide crystal 失效
标题翻译：氧化物晶体的制备方法
公开(公告)号：US5707441A
公开(公告)日：1998-01-13
申请号：US569895
申请日：1995-12-08
申请人： Yasuo Namikawa , Yuh Shiohara , Shoji Tanaka
发明人： Yasuo Namikawa , Yuh Shiohara , Shoji Tanaka
IPC分类号： C01G1/00 , C01G3/00 , C01G3/02 , C30B15/00 , C30B15/20 , C30B15/22 , C30B29/22 , H01B12/00 , H01B13/00
CPC分类号： C30B29/225 , C30B15/20 , Y10T117/1004
摘要： In order to prepare a large yttrium or lanthanoid based oxide superconductor crystal of higher quality, a method and an apparatus which can stably control the shape of a pulled crystal and stably maintain growth of the crystal from a melt are provided. A crystal of an oxide having a structure of RBa.sub.2 Cu.sub.3 O.sub.7-X (R: yttrium or lanthanoid element, 0.ltoreq.X.ltoreq.1) is pulled from a raw material melt which is stored in a crucible by a rotary crystal pulling shaft. During such pulling, a position of the surface of the raw material melt is measured with time to obtain a lowering speed of the surface in a direction substantially parallel to the crystal pulling direction, for adjusting the lifting speed of the crystal pulling shaft by this lowering speed.
摘要翻译：为了制备更高质量的大型钇或镧系氧化物超导体晶体，提供了可以稳定地控制拉晶体的形状并稳定地保持晶体从熔体生长的方法和装置。具有RBa2Cu3O7-X（R：钇或镧系元素，0

25. 发明授权

US08643065B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08643065B2
公开(公告)日：2014-02-04
申请号：US12919992
申请日：2009-12-11
申请人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
发明人： Kazuhiro Fujikawa , Hideto Tamaso , Shin Harada , Yasuo Namikawa
IPC分类号： H01L29/80
CPC分类号： H01L29/66068 , H01L21/0465 , H01L29/1066 , H01L29/1608 , H01L29/8083
摘要： A JFET is a semiconductor device allowing more reliable implementation of the characteristics essentially achievable by employing SiC as a material and includes a wafer having at least an upper surface made of silicon carbide, and a gate contact electrode formed on the upper surface. The wafer includes a first p-type region serving as an ion implantation region formed so as to include the upper surface. The first p-type region includes a base region disposed so as to include the upper surface, and a protruding region. The base region has a width (w1) in the direction along the upper surface greater than a width (w2) of the protruding region. The gate contact electrode is disposed in contact with the first p-type region such that the gate contact electrode is entirely located on the first p-type region as seen in plan view.
摘要翻译： JFET是半导体器件，允许更可靠地实现通过使用SiC作为材料而基本上可实现的特性，并且包括至少由碳化硅制成的上表面的晶片和形成在上表面上的栅极接触电极。晶片包括用作离子注入区域的第一p型区域，其形成为包括上表面。第一p型区域包括设置成包括上表面的基极区域和突出区域。基部区域沿着上表面的方向具有大于突出区域的宽度（w2）的宽度（w1）。栅极接触电极设置成与第一p型区域接触，使得栅极接触电极完全位于第一p型区域上，如平面图所示。

26. 发明申请

US20120161157A1 SILICON CARBIDE SUBSTRATE 审中-公开
标题翻译：碳化硅基板
公开(公告)号：US20120161157A1
公开(公告)日：2012-06-28
申请号：US13393235
申请日：2010-09-28
申请人： Hiroki Inoue , Shin Harada , Makoto Sasaki , Taro Nishiguchi , Kyoko Okita , Yasuo Namikawa
发明人： Hiroki Inoue , Shin Harada , Makoto Sasaki , Taro Nishiguchi , Kyoko Okita , Yasuo Namikawa
IPC分类号： H01L29/161
CPC分类号： H01L29/7802 , C30B29/36 , H01L21/02378 , H01L21/0243 , H01L21/02444 , H01L21/02447 , H01L21/0245 , H01L21/02529 , H01L21/02631 , H01L21/0475 , H01L29/1608 , H01L29/66068
摘要： A silicon carbide substrate, which achieves restrained warpage even when a different-type material layer made of a material other than silicon carbide, includes: a base layer made of silicon carbide; and a plurality of SiC layers arranged side by side on the base layer when viewed in a planar view and each made of single-crystal silicon carbide. A gap is formed between end surfaces of adjacent SiC layers.
摘要翻译：即使当由不同于碳化硅的材料制成的不同类型的材料层时也能实现约束翘曲的碳化硅衬底包括：由碳化硅制成的基底层; 以及在平面图中观察时，在基底层上并排设置的多个SiC层，并且均由单晶碳化硅构成。在相邻SiC层的端面之间形成间隙。

27. 发明申请

US20120061687A1 SILICON CARBIDE SUBSTRATE AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：碳化硅基板和半导体器件
公开(公告)号：US20120061687A1
公开(公告)日：2012-03-15
申请号：US13319599
申请日：2010-04-27
申请人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Yasuo Namikawa , Shinsuke Fujiwara
发明人： Shin Harada , Makoto Sasaki , Taro Nishiguchi , Yasuo Namikawa , Shinsuke Fujiwara
IPC分类号： H01L29/16
CPC分类号： H01L29/7802 , C30B23/00 , C30B29/36 , C30B33/06 , H01L21/02378 , H01L21/02529 , H01L21/2007 , H01L29/045 , H01L29/0878 , H01L29/1608 , H01L29/66068 , H01L29/7395
摘要： A silicon carbide substrate, which allows for reduced resistivity in the thickness direction thereof while restraining stacking faults from being produced due to heat treatment, includes: a base layer made of silicon carbide; and a SiC layer made of single-crystal silicon carbide and disposed on one main surface of the base layer. The base layer has an impurity concentration greater than 2×1019 cm−3. Further, the SiC layer has an impurity concentration greater than 5×1018 cm−3 and smaller than 2×1019 cm−3.
摘要翻译：一种碳化硅衬底，其允许在其抑制由于热处理而产生的堆垛层错的同时在其厚度方向上具有降低的电阻率，包括：由碳化硅制成的基底层; 以及由单晶碳化硅制成并设置在基层的一个主表面上的SiC层。基层的杂质浓度大于2×10 19 cm -3。此外，SiC层的杂质浓度大于5×10 18 cm -3，小于2×10 19 cm -3。

28. 发明申请

US20120056203A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20120056203A1
公开(公告)日：2012-03-08
申请号：US13320250
申请日：2010-04-27
申请人： Kazuhiro Fujikawa , Shin Harada , Taro Nishiguchi , Makoto Sasaki , Yasuo Namikawa , Shinsuke Fujiwara
发明人： Kazuhiro Fujikawa , Shin Harada , Taro Nishiguchi , Makoto Sasaki , Yasuo Namikawa , Shinsuke Fujiwara
IPC分类号： H01L29/12
CPC分类号： H01L29/1608 , H01L29/32 , H01L29/66068 , H01L29/808
摘要： A JFET, which is a semiconductor device allowing for reduced manufacturing cost, includes: a silicon carbide substrate; an active layer made of single-crystal silicon carbide and disposed on one main surface of the silicon carbide substrate; a source electrode disposed on the active layer; and a drain electrode formed on the active layer and separated from the source electrode. The silicon carbide substrate includes: a base layer made of single-crystal silicon carbide, and a SiC layer made of single-crystal silicon carbide and disposed on the base layer. The SiC layer has a defect density smaller than that of the base layer.
摘要翻译：作为允许降低制造成本的半导体器件的JFET包括：碳化硅衬底; 由单晶碳化硅构成的有源层，设置在碳化硅基板的一个主面上; 设置在所述有源层上的源电极; 以及形成在有源层上并与源电极分离的漏电极。碳化硅基板包括：由单晶碳化硅制成的基底层和由单晶碳化硅制成并设置在基底层上的SiC层。 SiC层的缺陷密度小于基底层的缺陷密度。

29. 发明申请

US20120015499A1 METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE 审中-公开
标题翻译：制造半导体基板的方法
公开(公告)号：US20120015499A1
公开(公告)日：2012-01-19
申请号：US13256328
申请日：2010-09-28
申请人： Makoto Sasaki , Shin Harada , Taro Nishiguchi , Kyoko Okita , Yasuo Namikawa
发明人： Makoto Sasaki , Shin Harada , Taro Nishiguchi , Kyoko Okita , Yasuo Namikawa
IPC分类号： H01L21/04
CPC分类号： H01L21/02667 , H01L21/02378 , H01L21/0243 , H01L21/02529 , H01L21/02612 , H01L21/02614 , H01L21/02656 , H01L21/047 , H01L21/0475 , H01L29/045 , H01L29/66068 , H01L29/7802
摘要： A combined substrate is prepared which has a supporting portion and first and second silicon carbide substrates. Between the first and second silicon carbide substrates, a gap having an opening exists. A closing layer for the gap is formed over the opening. The closing layer at least includes a silicon layer. In order to form a cover made of silicon carbide and closing the gap over the opening, the silicon layer is carbonized. By depositing sublimates from the first and second side surfaces of the first and second silicon carbide substrates onto the cover, a connecting portion is formed to close the opening. The cover is removed.
摘要翻译：制备具有支撑部分和第一和第二碳化硅衬底的组合衬底。在第一和第二碳化硅衬底之间，存在具有开口的间隙。在开口上形成用于间隙的闭合层。封闭层至少包括硅层。为了形成由碳化硅制成的盖子并且封闭开口上的间隙，硅层被碳化。通过将第一和第二碳化硅衬底的第一和第二侧表面的升华物沉积到盖上，形成连接部分以封闭开口。盖子被移除。

30. 发明申请

US20110278595A1 METHOD FOR MANUFACTURING SILICON CARBIDE SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, SILICON CARBIDE SUBSTRATE, AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译：制造碳化硅衬底的方法，制造半导体器件的方法，碳化硅衬底和半导体器件
公开(公告)号：US20110278595A1
公开(公告)日：2011-11-17
申请号：US13104275
申请日：2011-05-10
申请人： Taro Nishiguchi , Makoto Sasaki , Shin Harada , Kyoko Okita , Hiroki Inoue , Yasuo Namikawa
发明人： Taro Nishiguchi , Makoto Sasaki , Shin Harada , Kyoko Okita , Hiroki Inoue , Yasuo Namikawa
IPC分类号： H01L29/24 , C30B23/02 , H01L21/20 , B32B13/04
CPC分类号： H01L29/7802 , B32B9/00 , B32B13/04 , B32B2307/202 , B32B2307/732 , B32B2457/14 , C30B29/36 , C30B33/06 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02631 , H01L21/046 , H01L21/049 , H01L21/2007 , H01L29/045 , H01L29/1608 , H01L29/66068
摘要： A method for manufacturing a silicon carbide substrate includes the steps of: preparing a base substrate made of silicon carbide and a SiC substrate made of single-crystal silicon carbide; fabricating a stacked substrate by placing said SiC substrate on and in contact with a main surface of said base substrate; and connecting said base substrate and said SiC substrate to each other by heating said stacked substrate in a container to fall within a range of temperature equal to or greater than a sublimation temperature of silicon carbide constituting said base substrate. In the step of connecting said base substrate and said SiC substrate, a silicon carbide body made of silicon carbide and different from said base substrate and said SiC substrate is disposed in said container.
摘要翻译：制造碳化硅基板的方法包括以下步骤：制备由碳化硅制成的基底基板和由单晶碳化硅制成的SiC基板; 通过将所述SiC衬底放置在所述基底衬底的主表面上并与之接触来制造堆叠衬底; 以及通过在容器中加热所述堆叠的基板而将所述基底基板和所述SiC基板彼此连接，以落入构成所述基底基板的碳化硅的升华温度以上的温度范围内。在连接所述基底衬底和所述SiC衬底的步骤中，将由碳化硅制成并且与所述基底衬底和所述SiC衬底不同的碳化硅体设置在所述容器中。

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