专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US09208873B2 Non-volatile storage system biasing conditions for standby and first read 有权
公开(公告)号：US09208873B2
公开(公告)日：2015-12-08
申请号：US14700134
申请日：2015-04-29
申请人： SANDISK 3D LLC
发明人： Chang Siau
IPC分类号： G11C16/10 , G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C16/10 , G11C2013/005 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149
摘要： Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set to ground. During transition of the memory array from the standby mode to a read mode, a selected word line comb may be set to a read voltage while the unselected word lines and the bit lines remain at ground. During the read mode, memory cells connected to the selected bit lines and the selected word line comb may be sensed while the selected bit lines are biased to a selected bit line voltage equal to or close to ground and the unselected bit lines are left floating after initially being set to ground.

22. 发明授权

US09171584B2 Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines 有权
标题翻译：具有垂直位线上方和下方交错垂直选择器件的三维非易失性存储器
公开(公告)号：US09171584B2
公开(公告)日：2015-10-27
申请号：US13886874
申请日：2013-05-03
申请人： SANDISK 3D LLC
发明人： Roy E. Scheuerlein , Chang Siau
IPC分类号： G11C11/00 , G11C5/06 , G11C13/00 , H01L27/24 , G11C7/18 , H01L45/00
CPC分类号： G11C5/06 , G11C5/063 , G11C7/18 , G11C13/0023 , G11C13/003 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146
摘要： A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.
摘要翻译：存储元件的三维阵列响应于在其上施加的一个或多个电压差而可逆地改变电导/电阻的水平。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的局部位线从衬底垂直定向并穿过多个平面。垂直定向选择器件用于将局部位线连接到全局位线。垂直取向的选择装置的第一子集位于垂直取向的位线上方，垂直取向的选择装置的第二子集（与垂直取向的选择装置的第一子集交错）位于垂直取向的位线下方。

23. 发明申请

US20140254242A1 NON-VOLATILE STORAGE SYSTEM BIASING CONDITIONS FOR STANDBY AND FIRST READ 有权
标题翻译：非易失存储系统偏好条件用于待机和第一次读取
公开(公告)号：US20140254242A1
公开(公告)日：2014-09-11
申请号：US14197136
申请日：2014-03-04
申请人： SANDISK 3D LLC
发明人： Chang Siau
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C16/10 , G11C2013/005 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149
摘要： Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set to ground. During transition of the memory array from the standby mode to a read mode, a selected word line comb may be set to a read voltage while the unselected word lines and the bit lines remain at ground. During the read mode, memory cells connected to the selected bit lines and the selected word line comb may be sensed while the selected bit lines are biased to a selected bit line voltage equal to or close to ground and the unselected bit lines are left floating after initially being set to ground.
摘要翻译：描述了用于降低非易失性存储系统的功耗并减少第一读延迟的方法。非易失性存储系统可以包括交叉点存储器阵列。在一些实施例中，在待机模式期间，存储器阵列可被偏置，使得字线和位线都被设置为接地。在存储器阵列从待机模式转换到读取模式期间，所选择的字线梳可以被设置为读取电压，而未选择的字线和位线保持在地。在读取模式期间，可以感测连接到所选位线和所选择的字线梳的存储单元，同时所选择的位线被偏置到等于或接近地的选定位线电压，并且未选择的位线在最初被置于地面。

24. 发明申请

US20130308363A1 THREE DIMENSIONAL NON-VOLATILE STORAGE WITH INTERLEAVED VERTICAL SELECT DEVICES ABOVE AND BELOW VERTICAL BIT LINES 有权
标题翻译：三维非易失性存储器，具有上述垂直选择器件和下面的垂直位线
公开(公告)号：US20130308363A1
公开(公告)日：2013-11-21
申请号：US13886874
申请日：2013-05-03
申请人： SANDISK 3D LLC
发明人： Roy E. Scheuerlein , Chang Siau
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G11C5/063 , G11C7/18 , G11C13/0023 , G11C13/003 , G11C2213/71 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/142 , H01L45/143 , H01L45/146
摘要： A three-dimensional array of memory elements reversibly change a level of electrical conductance/resistance in response to one or more voltage differences being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Local bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes. Vertically oriented select devices are used to connect the local bit lines to global bit lines. A first subset of the vertically oriented select devices are positioned above the vertically oriented bit lines and a second subset of the vertically oriented select devices (interleaved with the first subset of the vertically oriented select devices) are positioned below the vertically oriented bit lines.
摘要翻译：存储元件的三维阵列响应于在其上施加的一个或多个电压差而可逆地改变电导/电阻的水平。存储元件跨越位于半导体衬底上方不同距离的多个平面形成。所有平面的存储元件连接到的局部位线从衬底垂直定向并穿过多个平面。垂直定向选择器件用于将局部位线连接到全局位线。垂直取向的选择装置的第一子集位于垂直取向的位线上方，垂直取向的选择装置的第二子集（与垂直取向的选择装置的第一子集交错）位于垂直取向的位线下方。

25. 发明授权

US09646691B2 Monolithic three dimensional memory arrays with staggered vertical bit lines and dual-gate bit line select transistors 有权
公开(公告)号：US09646691B2
公开(公告)日：2017-05-09
申请号：US14522777
申请日：2014-10-24
申请人： SanDisk 3D LLC
发明人： Chang Siau
IPC分类号： G11C11/00 , G11C11/34 , G11C13/00 , H01L45/00 , H01L27/24
CPC分类号： G11C13/0069 , G11C13/0026 , G11C2213/71 , G11C2213/77 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/10 , H01L45/1226 , H01L45/145 , H01L45/146
摘要： A monolithic three-dimensional memory array is provided that includes global bit lines disposed above a substrate, each global bit line having a long axis, vertically-oriented bit lines disposed above the global bit lines, word lines disposed above the global bit lines, memory cells coupled between the vertically-oriented bit lines and the word lines, and vertically-oriented bit line select transistors coupled between the vertically-oriented bit lines and the global bit lines. Each vertically-oriented bit line select transistor has a width, a first control terminal and a second control terminal. The word lines and the vertically-oriented bit lines have a half-pitch, and the width of the vertically-oriented bit line select transistors is between about two times the half-pitch and about three times the half-pitch. Vertical bit lines disposed above adjacent global bit lines are offset from one another in a direction along the long axis of the global bit lines.

26. 发明授权

US09472280B2 Vertical cross point reram forming method 有权
公开(公告)号：US09472280B2
公开(公告)日：2016-10-18
申请号：US14732766
申请日：2015-06-07
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.

27. 发明申请

US20160133320A1 SENSE AMPLIFIER INCLUDING A SINGLE-TRANSISTOR AMPLIFIER AND LEVEL SHIFTER AND METHODS THEREFOR 有权
标题翻译：包括单晶体放大器和电平变换器的感应放大器及其方法
公开(公告)号：US20160133320A1
公开(公告)日：2016-05-12
申请号：US14539150
申请日：2014-11-12
申请人： SanDisk 3D LLC
发明人： Chang Siau , Yingchang Chen
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/067 , G11C13/0002 , G11C13/0023 , G11C13/0061 , G11C27/024 , G11C2013/0054 , G11C2213/71
摘要： Methods are provided for use with a memory array that includes a selected memory cell coupled to a selected word line and a selected bit line, with the selected word line biased at a read voltage. The method include coupling a sense amplifier to the selected bit line, the sense amplifier including a capacitor integrator, a single-transistor amplifier and a level shifter, maintaining the selected bit line at a voltage of substantially 0V using the single-transistor amplifier and the level shifter, and integrating a selected bit line current on the capacitor integrator.
摘要翻译：提供了与存储器阵列一起使用的方法，所述存储器阵列包括耦合到所选择的字线和选定位线的所选择的存储器单元，所选择的字线被偏置在读取电压。该方法包括将感测放大器耦合到所选择的位线，读出放大器包括电容器积分器，单晶体管放大器和电平转换器，使用单晶体管放大器将所选位线保持在大致0V的电压，并且电平移位器，并将所选位线电流积分到电容积分器上。

28. 发明申请

US20160093373A1 APPARATUS AND METHODS FOR SENSING HARD BIT AND SOFT BITS 有权
公开(公告)号：US20160093373A1
公开(公告)日：2016-03-31
申请号：US14500476
申请日：2014-09-29
申请人： SanDisk 3D LLC
发明人： Chang Siau , Jeffrey Koon Yee Lee , Tianhong Yan , Yingchang Chen , Gopinath Balakrishnan , Tz-yi Liu
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0028 , G11C13/0061 , G11C16/28 , G11C16/32 , G11C27/02 , G11C2013/0054
摘要： A method is provided for reading a memory cell of a nonvolatile memory system. The method includes generating a hard bit and N soft bits for the memory cell in a total time corresponding to a single read latency period and N+1 data transfer times.

29. 发明申请

US20150269998A1 VERTICAL CROSS POINT RERAM FORMING METHOD 有权
标题翻译：垂直交叉点RERAM形成方法
公开(公告)号：US20150269998A1
公开(公告)日：2015-09-24
申请号：US14732766
申请日：2015-06-07
申请人： SanDisk 3D LLC
发明人： Chang Siau , Tianhong Yan
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0097 , G11C2213/71 , G11C2213/77
摘要： Methods for forming non-volatile storage elements in a non-volatile storage system are described. In some embodiments, a plurality of forming operations may be performed in which non-volatile storage elements located near the far end of a plurality of word line fingers associated with a word line comb are formed prior to forming other non-volatile storage elements. In one example, non-volatile storage elements may be formed in each of the plurality of word line fingers in parallel and in an order that forms non-volatile storage elements in each of the plurality of word line fingers that are located near the far ends of the plurality of word line fingers before forming other non-volatile storage elements. Each non-volatile storage element that is formed during a forming operation may be current limited while a forming voltage is applied across the non-volatile storage element.
摘要翻译：描述了在非易失性存储系统中形成非易失性存储元件的方法。在一些实施例中，可以执行多个形成操作，其中在形成其他非易失性存储元件之前形成位于与字线梳相关联的多个字线手指的远端附近的非易失性存储元件。在一个示例中，非易失性存储元件可以并行地形成在多个字线手指中的每一个中，并且以在多个字线手指中的远端附近形成非易失性存储元件的顺序在形成其他非易失性存储元件之前的多个字线指。在成形操作期间形成的每个非易失性存储元件可以是电流限制的，同时在非易失性存储元件上施加形成电压。

30. 发明申请

US20150248933A1 NON-VOLATILE STORAGE SYSTEM BIASING CONDITIONS FOR STANDBY AND FIRST READ 有权
标题翻译：非易失存储系统偏好条件用于待机和第一次读取
公开(公告)号：US20150248933A1
公开(公告)日：2015-09-03
申请号：US14700134
申请日：2015-04-29
申请人： SANDISK 3D LLC
发明人： Chang Siau
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C13/0026 , G11C16/10 , G11C2013/005 , G11C2213/71 , G11C2213/79 , H01L27/2436 , H01L27/2454 , H01L27/249 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/149
摘要： Methods for reducing power consumption of a non-volatile storage system and reducing first read latency are described. The non-volatile storage system may include a cross-point memory array. In some embodiments, during a standby mode, the memory array may be biased such that both word lines and bit lines are set to ground. During transition of the memory array from the standby mode to a read mode, a selected word line comb may be set to a read voltage while the unselected word lines and the bit lines remain at ground. During the read mode, memory cells connected to the selected bit lines and the selected word line comb may be sensed while the selected bit lines are biased to a selected bit line voltage equal to or close to ground and the unselected bit lines are left floating after initially being set to ground.
摘要翻译：描述了用于降低非易失性存储系统的功耗并减少第一读延迟的方法。非易失性存储系统可以包括交叉点存储器阵列。在一些实施例中，在待机模式期间，存储器阵列可被偏置，使得字线和位线都被设置为接地。在将存储器阵列从待机模式转换到读取模式期间，所选择的字线梳可以被设置为读取电压，而未选择的字线和位线保持在地。在读取模式期间，可以感测连接到所选位线和所选择的字线梳的存储单元，同时所选择的位线被偏置到等于或接近地的选定位线电压，并且未选择的位线在最初被置于地面。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式