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21. 发明授权

US07804706B2 Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication 有权
标题翻译：用于MRAM器件制造中的超薄层间电介质方法的底电极掩模设计
公开(公告)号：US07804706B2
公开(公告)日：2010-09-28
申请号：US12313117
申请日：2008-11-17
申请人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao
发明人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , G03F1/36 , H01L27/0207 , H01L43/12 , Y10S977/935
摘要： A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer.
摘要翻译：公开了底部电极（BE）布局，其具有在多个器件块中重复的四个不同部分，并且用于对MRAM中的BE层进行图案化。器件部分包括具有基本相同形状和尺寸的BE形状和虚拟BE形状并且覆盖基本部分的大部分。在多个虚拟BE形状中存在通孔，其中每个通孔将在WL焊盘上对准。第二接合焊盘部分包括具有多个通孔的不透明区域。剩下的两部分涉及MRAM中的开放场地区。第三部分具有多个具有第一区域尺寸的虚拟BE形状。第四部分具有多个具有大于第一区域尺寸的第二区域尺寸的虚拟BE形状，以提供更底层的蚀刻停止层ILD层的更完整的BE覆盖。

22. 发明申请

US20100109106A1 High density spin-transfer torque MRAM process 有权
标题翻译：高密度自旋转移力矩MRAM工艺
公开(公告)号：US20100109106A1
公开(公告)日：2010-05-06
申请号：US12290495
申请日：2008-10-31
申请人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao , Adam Zhong , Wai-Ming Johnson Kan , Daniel Liu
发明人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao , Adam Zhong , Wai-Ming Johnson Kan , Daniel Liu
IPC分类号： H01L29/82 , H01L21/00
CPC分类号： H01L27/228 , H01L43/12
摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.
摘要翻译：公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

23. 发明申请

US20090209102A1 Use of CMP to contact a MTJ structure without forming a via 有权
标题翻译：使用CMP接触MTJ结构而不形成通孔
公开(公告)号：US20090209102A1
公开(公告)日：2009-08-20
申请号：US12070286
申请日：2008-02-14
申请人： Adam Zhong , Wai-Ming Kan , Tom Zhong , Chyu-Jiuh Torng
发明人： Adam Zhong , Wai-Ming Kan , Tom Zhong , Chyu-Jiuh Torng
IPC分类号： H01L21/302
CPC分类号： H01L21/31053 , H01L43/12
摘要： A process is described for making contact to the buried capping layers of GMR and MTJ devices without the need to form and fill via holes. CMP is applied to the structure in three steps: (1) conventional CMP (2) a Highly Selective Slurry (HSS) is substituted for the conventional slurry to just expose the capping layer, and (3) the HSS is diluted and used to clean the surface as well as to cause a slight protrusion of the capping layers above the surrounding dielectric surface, making it easier the contact them without damaging the devices below.
摘要翻译：描述了与GMR和MTJ装置的掩埋覆盖层接触而不需要形成和填充通孔的方法。 CMP结构分为三个步骤：（1）常规CMP（2）采用高选择性浆料（HSS）代替传统的浆料，仅暴露顶盖层，（3）将HSS稀释并用于清洗表面以及使覆盖层在周围的电介质表面上稍微突出，使得更容易接触它们而不损坏下面的器件。

24. 发明申请

US20090104718A1 Method of magnetic tunneling layer processes for spin-transfer torque MRAM 有权
标题翻译：旋转转矩MRAM的磁隧道层工艺方法
公开(公告)号：US20090104718A1
公开(公告)日：2009-04-23
申请号：US11975045
申请日：2007-10-17
申请人： Tom Zhong , Rongfu Xiao , Chyu-Jiuh Torng , Adam Zhong
发明人： Tom Zhong , Rongfu Xiao , Chyu-Jiuh Torng , Adam Zhong
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.
摘要翻译：公开了一种用于在STT-MRAM中形成MTJ的方法，其中容易轴CD独立于硬轴CD来确定。一种方法涉及两个光刻步骤和两个蚀刻步骤，以在通过第三蚀刻工艺通过MTJ叠层堆叠的硬掩模中形成柱。可选地，第三蚀刻可以在隧道势垒上或在自由层中停止。第二实施例涉及在硬掩模层上形成第一平行线图案，并通过第一蚀刻步骤通过MTJ堆叠传送线图案。平面绝缘层与线图案中的侧壁相邻地形成，然后形成第二平行线图案，其通过第二次蚀刻通过MTJ叠层转印以形成柱形图案。蚀刻终点可以独立控制硬轴和易轴尺寸。

25. 发明授权

US07508700B2 Method of magnetic tunneling junction pattern layout for magnetic random access memory 有权
标题翻译：磁性随机存取存储器磁隧道结图案布局方法
公开(公告)号：US07508700B2
公开(公告)日：2009-03-24
申请号：US11724435
申请日：2007-03-15
申请人： Tom Zhong , Terry Kin Ting Ko , Chyu-Jiuh Torng , Wai-Ming Kan , Adam Zhong
发明人： Tom Zhong , Terry Kin Ting Ko , Chyu-Jiuh Torng , Wai-Ming Kan , Adam Zhong
IPC分类号： G11C11/00
CPC分类号： H01L27/222 , H01L43/12 , Y10S977/935
摘要： An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer.
摘要翻译：公开了一种用于存储器件的MTJ图案布局，其包括主动MTJ器件块之外的两个CMP辅助特征。第一组多个虚拟MTJ设备位于形成在活动MTJ设备块周围的两个虚拟带中。内部虚拟带通过MTJ ILD层与外部虚拟带分离，并且具有与MTJ器件块基本相同的MTJ器件密度。外虚拟带具有比内虚拟带大至少10％的MTJ装置密度。内部虚拟带用于最小化MTJ器件块中的CMP边缘效应，而外部虚拟带改善了平坦化。在外虚拟带外部的接触焊盘中采用第二多个虚拟MTJ器件，并且形成在WL ILD层和BIT ILD层之间，从而最小化MTJ ILD层的分层。

26. 发明授权

US07122386B1 Method of fabricating contact pad for magnetic random access memory 有权
标题翻译：制造磁性随机存取存储器接触焊盘的方法
公开(公告)号：US07122386B1
公开(公告)日：2006-10-17
申请号：US11231674
申请日：2005-09-21
申请人： Chyu-Jiuh Torng , Tom Zhong , Wei Cao , Po-Kang Wang
发明人： Chyu-Jiuh Torng , Tom Zhong , Wei Cao , Po-Kang Wang
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222
摘要： A method of forming a Cu—Cu junction between a word line pad (WLP) and bit line (BL) contact is described. An opening above a WL contact is formed in a first SiNx layer on a substrate that includes a WLP and word line. After a bottom electrode (BE) layer, MTJ stack, and hard mask are sequentially deposited, an etch forms an MTJ element above the word line. Another etch forms a BE and exposes the first SiNx layer above the WLP and bond pad (BP). An MTJ ILD layer is deposited and planarized followed by deposition of a second SiNx layer and BL ILD layer. Trenches are formed in the BL ILD layer and second SiNx layer above the WLP, hard mask and BP. After vias are formed in the MTJ ILD and first SiNx layers above the WLP and BP, Cu deposition follows to form dual damascene BL contacts.
摘要翻译：描述了在字线焊盘（WLP）和位线（BL）触点之间形成Cu-Cu结的方法。在包括WLP和字线的衬底上的第一SiN x层中形成WL触点上方的开口。在底电极（BE）层，MTJ叠层和硬掩模之后，顺序沉积，蚀刻在字线之上形成MTJ元件。另一蚀刻形成BE，并使WLP和接合焊盘（BP）上方的第一SiN x层暴露。沉积MTJ ILD层并平坦化，随后沉积第二SiN x层和BL ILD层。沟槽形成在WLP，硬掩模和BP之上的BL ILD层和第二SiN x x层中。在WLP和BP上方的MTJ ILD和第一SiN x x层中形成通孔之后，随后进行Cu沉积以形成双镶嵌BL触点。

27. 发明授权

US08183061B2 High density spin-transfer torque MRAM process 有权
标题翻译：高密度自旋转移力矩MRAM工艺
公开(公告)号：US08183061B2
公开(公告)日：2012-05-22
申请号：US12931648
申请日：2011-02-07
申请人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao , Adam Zhong , Wai-Ming Johnson Kan , Daniel Liu
发明人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao , Adam Zhong , Wai-Ming Johnson Kan , Daniel Liu
IPC分类号： H01L21/441
CPC分类号： H01L27/228 , H01L43/12
摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.
摘要翻译：公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

28. 发明授权

US08133745B2 Method of magnetic tunneling layer processes for spin-transfer torque MRAM 有权
标题翻译：旋转转矩MRAM的磁隧道层工艺方法
公开(公告)号：US08133745B2
公开(公告)日：2012-03-13
申请号：US11975045
申请日：2007-10-17
申请人： Tom Zhong , Rongfu Xiao , Chyu-Jiuh Torng , Adam Zhong
发明人： Tom Zhong , Rongfu Xiao , Chyu-Jiuh Torng , Adam Zhong
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , B82Y10/00 , H01L27/228
摘要： A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.
摘要翻译：公开了一种用于在STT-MRAM中形成MTJ的方法，其中容易轴CD独立于硬轴CD来确定。一种方法涉及两个光刻步骤和两个蚀刻步骤，以在通过第三蚀刻工艺通过MTJ叠层堆叠的硬掩模中形成柱。可选地，第三蚀刻可以在隧道势垒上或在自由层中停止。第二实施例涉及在硬掩模层上形成第一平行线图案，并通过第一蚀刻步骤通过MTJ堆叠传送线图案。平面绝缘层与线图案中的侧壁相邻地形成，然后形成第二平行线图案，其通过第二次蚀刻通过MTJ叠层转印以形成柱形图案。蚀刻终点可以独立控制硬轴和易轴尺寸。

29. 发明申请

US20110129946A1 High density spin-transfer torque MRAM process 有权
公开(公告)号：US20110129946A1
公开(公告)日：2011-06-02
申请号：US12931648
申请日：2011-02-07
申请人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao , Adam Zhong , Wai-Ming Johnson Kan , Daniel Liu
发明人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao , Adam Zhong , Wai-Ming Johnson Kan , Daniel Liu
IPC分类号： H01L21/00
CPC分类号： H01L27/228 , H01L43/12
摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

30. 发明申请

US20100123207A1 Bottom electrode mask design for ultra-thin interlayer dielectric approach in MRAM device fabrication 有权
公开(公告)号：US20100123207A1
公开(公告)日：2010-05-20
申请号：US12313117
申请日：2008-11-17
申请人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao
发明人： Tom Zhong , Chyu-Jiuh Torng , Rongfu Xiao
IPC分类号： H01L29/82 , H01L21/00 , G03F1/00
CPC分类号： H01L27/222 , G03F1/36 , H01L27/0207 , H01L43/12 , Y10S977/935
摘要： A bottom electrode (BE) layout is disclosed that has four distinct sections repeated in a plurality of device blocks and is used to pattern a BE layer in a MRAM. A device section includes BE shapes and dummy BE shapes with essentially the same shape and size and covering a substantial portion of substrate. There is a via in a plurality of dummy BE shapes where each via will be aligned over a WL pad. A second bonding pad section comprises an opaque region having a plurality of vias. The remaining two sections relate to open field regions in the MRAM. The third section has a plurality of dummy BE shapes with a first area size. The fourth section has a plurality of dummy BE shapes with a second area size greater than the first area size to provide more complete BE coverage of an underlying etch stop ILD layer.

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