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21. 发明申请

US20080006876A1 STACKING FAULT REDUCTION IN EPITAXIALLY GROWN SILICON 有权
标题翻译：封装在外延硅中的故障减少
公开(公告)号：US20080006876A1
公开(公告)日：2008-01-10
申请号：US11456326
申请日：2006-07-10
申请人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
发明人： Yun-Yu Wang , Linda Black , Judson R. Holt , Woo-Hyeong Lee , Scott Luning , Christopher D. Sheraw
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L21/02639 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/84
摘要： Methods and a structure are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.
摘要翻译：公开了用于提供用于混合表面取向结构的堆垛层错缺陷外延生长的硅的方法和结构。在一个实施例中，一种方法包括在开口中的氧化硅衬垫上沉积氮化硅衬垫，蚀刻以除去开口的下表面上的氧化硅衬垫和氮化硅衬垫，将邻近下表面的氮化硅衬垫并且在开口中外延生长硅。由于底切产生的负斜率，硅片堆积层错误大大减少。

22. 发明申请

US20060292852A1 BACK END INTERCONNECT WITH A SHAPED INTERFACE 失效
标题翻译：后端互连与形状接口
公开(公告)号：US20060292852A1
公开(公告)日：2006-12-28
申请号：US11463447
申请日：2006-08-09
申请人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
发明人： Lawrence Clevenger , Andrew Cowley , Timothy Dalton , Mark Hoinkis , Steffen Kaldor , Erdem Kaltalioglu , Kaushik Kumar , Douglas La Tulipe , Jochen Schacht , Andrew Simon , Terry Spooner , Yun-Yu Wang , Clement Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.
摘要翻译：在集成电路的线的后端中的互连结构通过在锥形孔中去除下互连的顶表面中的材料而形成连续层之间的接触，该去除过程延伸穿过上孔的衬垫，以及沉积向下延伸到锥形孔中的第二衬垫，从而增加接触件的机械强度，从而提高集成电路的整体可靠性。

23. 发明授权

US07122462B2 Back end interconnect with a shaped interface 有权
公开(公告)号：US07122462B2
公开(公告)日：2006-10-17
申请号：US10707122
申请日：2003-11-21
申请人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Andrew P. Cowley , Timothy J. Dalton , Mark Hoinkis , Steffen K. Kaldor , Erdem Kaltalioglu , Kaushik A. Kumar , Douglas C. La Tulipe, Jr. , Jochen Schacht , Andrew H. Simon , Terry A. Spooner , Yun-Yu Wang , Clement H. Wann , Chih-Chao Yang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76844 , H01L21/76805 , H01L21/76807 , H01L21/76814 , H01L21/76846 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in the back end of the line of an integrated circuit forms contacts between successive layers by removing material in the top surface of the lower interconnect in a cone-shaped aperture, the removal process extending through the liner of the upper aperture, and depositing a second liner extending down into the cone-shaped aperture, thereby increasing the mechanical strength of the contact, which then enhance the overall reliability of the integrated circuit.

24. 发明授权

US07102232B2 Structure to improve adhesion between top CVD low-k dielectric and dielectric capping layer 有权
标题翻译：结构以改善顶部CVD低介电常数介电层和电介质顶盖层之间的附着力
公开(公告)号：US07102232B2
公开(公告)日：2006-09-05
申请号：US10827693
申请日：2004-04-19
申请人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
发明人： Lawrence A. Clevenger , Stefanie R. Chiras , Timothy Dalton , James J. Demarest , Derren N. Dunn , Chester T. Dziobkowski , Philip L. Flaitz , Michael W. Lane , James R. Lloyd , Darryl D. Restaino , Thomas M. Shaw , Yun-Yu Wang , Chih-Chao Yang
IPC分类号： H01L23/52
CPC分类号： H01L21/02126 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02315 , H01L21/02362 , H01L21/31633 , H01L21/76826 , H01L21/76829 , H01L21/76832 , H01L21/76834 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure in which the adhesion between an upper level low-k dielectric material, such as a material comprising elements of Si, C, O, and H, and an underlying diffusion capping dielectric, such as a material comprising elements of C, Si, N and H, is improved by incorporating an adhesion transition layer between the two dielectric layers. The presence of the adhesion transition layer between the upper level low-k dielectric and the diffusion barrier capping dielectric can reduce the chance of delamination of the interconnect structure during the packaging process. The adhesion transition layer provided herein includes a lower SiOx— or SiON-containing region and an upper C graded region. Methods of forming such a structure, in particularly the adhesion transition layer, are also provided.
摘要翻译：一种互连结构，其中上层低k介电材料（例如包含Si，C，O和H的元素的材料）与下面的扩散覆盖电介质（例如包含C，Si元素的材料）之间的粘合通过在两个电介质层之间引入粘附过渡层来改善N和H。在上层低k电介质和扩散阻挡覆盖电介质之间的粘附过渡层的存在可以减少在包装过程中互连结构的分层的可能性。本文提供的粘合过渡层包括含低级SiO x - 或SiON的区域和上C级分区域。还提供了形成这种结构，特别是粘附过渡层的方法。

25. 发明申请

US20060108609A1 Barrier Dielectric Stack for Seam Protection 失效
标题翻译：用于接缝保护的阻隔电介质堆叠
公开(公告)号：US20060108609A1
公开(公告)日：2006-05-25
申请号：US10904661
申请日：2004-11-22
申请人： Brett Engel , Stephen Lucarini , John Sylvestri , Yun-Yu Wang
发明人： Brett Engel , Stephen Lucarini , John Sylvestri , Yun-Yu Wang
IPC分类号： H01L29/76
CPC分类号： H01L23/3192 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： The present invention provides a semiconducting device including a gate dielectric atop a semiconducting substrate, the semiconducting substrate containing source and drain regions adjacent the gate dielectric; a gate conductor atop the gate dielectric; a conformal dielectric passivation stack positioned on at least the gate conductor sidewalls, the conformal dielectric passivation stack comprising a plurality of conformal dielectric layers, wherein no electrical path extends entirely through the stack; and a contact to the source and drain regions, wherein the discontinuous seam through the conformal dielectric passivation stack substantially eliminates shorting between the contact and the gate conductor. The present invention also provides a method for forming the above-described semiconducting device.
摘要翻译：本发明提供一种半导体器件，其包括在半导体衬底顶部的栅极电介质，所述半导体衬底含有邻近栅极电介质的源区和漏区; 栅极电介质顶部的栅极导体; 位于至少栅极导体侧壁上的保形介质钝化堆叠，所述保形介质钝化堆叠包括多个保形介电层，其中没有电路完全穿过堆叠; 以及与源区和漏区的接触，其中通过保形电介质钝化堆的不连续接缝基本上消除了接触和栅极导体之间的短路。本发明还提供了形成上述半导体器件的方法。

26. 发明申请

US20050200024A1 Method to generate porous organic dielectric 失效
标题翻译：生成多孔有机电介质的方法
公开(公告)号：US20050200024A1
公开(公告)日：2005-09-15
申请号：US11125549
申请日：2005-05-10
申请人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
发明人： Lawrence Clevenger , Stephen Greco , Keith Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).
摘要翻译：本发明提供一种形成集成电路结构中的布线层的方法，该集成电路结构形成有机绝缘体，图案化绝缘体，将衬垫沉积在绝缘体上，并将该结构暴露于等离子体，以在绝缘体旁边的区域中形成孔衬垫。衬垫形成得足够薄以允许等离子体穿过衬垫并在绝缘体中形成孔。在等离子体处理期间，等离子体通过衬垫而不影响衬垫。在等离子体处理之后，可以沉积另外的衬里材料。此后，导体被沉积，导体的多余部分从结构中移除，使得导体仅保留在绝缘体的图案化部分内。该方法产生集成电路结构，其具有具有图案化特征的有机绝缘体，衬里图案化特征的衬垫和填充图案化特征的导体。绝缘体包括与绝缘体的表面区域相接触的孔，该孔与衬垫接触，并且孔仅沿着与衬垫接触的表面区域（衬里不在孔内）存在。

27. 发明授权

US06921978B2 Method to generate porous organic dielectric 失效
公开(公告)号：US06921978B2
公开(公告)日：2005-07-26
申请号：US10249799
申请日：2003-05-08
申请人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
发明人： Lawrence A. Clevenger , Stephen E. Greco , Keith T. Kwietniak , Soon-Cheon Seo , Chih-Chao Yang , Yun-Yu Wang , Kwong H. Wong
IPC分类号： H01L21/312 , H01L21/4763 , H01L21/768 , H01L23/48 , H01L23/52 , H01L23/522
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76814 , H01L21/7682 , H01L21/76826 , H01L21/76835 , H01L21/76856 , H01L2221/1036
摘要： The invention provides a method of forming a wiring layer in an integrated circuit structure that forms an organic insulator, patterns the insulator, deposits a liner on the insulator, and exposes the structure to a plasma to form pores in the insulator in regions next to the liner. The liner is formed thin enough to allow the plasma to pass through the liner and form the pores in the insulator. During the plasma processing, the plasma passes through the liner without affecting the liner. After the plasma processing, additional liner material may be deposited. After this, a conductor is deposited and excess of portions of the conductor are removed from the structure such that the conductor only remains within patterned portions of the insulator. This method produces an integrated circuit structure that has an organic insulator having patterned features, a liner lining the patterned features, and a conductor filling the patterned features. The insulator includes pores along surface areas of the insulator that are in contact with the liner and the pores exist only along the surface areas that are in contact with the liner (the liner is not within the pores).

28. 发明授权

US06661097B1 Ti liner for copper interconnect with low-k dielectric 失效
标题翻译：用于低k电介质的铜互连的Ti衬垫
公开(公告)号：US06661097B1
公开(公告)日：2003-12-09
申请号：US10287155
申请日：2002-11-01
申请人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
发明人： Larry Clevenger , Stanley J. Klepeis , Hsiao-Ling Lu , Jeffrey R. Marino , Andrew Herbert Simon , Yun-Yu Wang , Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , H01L21/76846 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.
摘要翻译：在铜后端集成电路技术中，使用低k有机基层间电介质的先进技术具有碳污染的问题，在使用氧化物作为电介质的电路中不会发生这种问题。用于铜线的复合衬里层使用Ti作为底层，其具有吸除碳和其它污染物的性质。通过添加一层分离Ti和铜的TiN层，避免了与铜反应形成高电阻率化合物的Ti的已知问题。

29. 发明授权

US06380628B2 Microstructure liner having improved adhesion 失效
标题翻译：显微组织衬垫具有改进的粘合性
公开(公告)号：US06380628B2
公开(公告)日：2002-04-30
申请号：US09377329
申请日：1999-08-18
申请人： John A. Miller , Andrew Simon , Jill Slattery , Cyprian E. Uzoh , Yun-Yu Wang
发明人： John A. Miller , Andrew Simon , Jill Slattery , Cyprian E. Uzoh , Yun-Yu Wang
IPC分类号： H01L2348
CPC分类号： H01L21/76862 , H01L21/76816 , H01L21/76843 , H01L21/76865 , H01L21/76871
摘要： A damascene structure, such as a conductive line or via, having a liner with a roughened surface between the substrate and the conductive fill and, preferably, a smooth bottom. The substrate underneath the liner may also have a roughened sidewall and smooth bottom. Such a structure provides enhanced adhesion between one or more layers of the damascene structure. The damascene structure may be manufactured by applying a photoresist over a substrate top surface, exposing the photoresist under conditions that create a standing wave in the resist, and developing the photoresist to provide a pattern having the desired roughened or serrated outline. The pattern is transferred into the substrate, the liner is applied over the substrate bottom and sidewalls, and the liner is filled with conductive material. A roughened liner surface may be achieved by applying a partial layer of liner material over the substrate, removing a portion of the partial layer, and repeating the application and removal steps.
摘要翻译：具有在衬底和导电填料之间具有粗糙表面的衬垫，以及优选光滑底部的镶嵌结构，例如导电线或通孔。衬垫下面的衬底也可以具有粗糙的侧壁和光滑的底部。这种结构提供了镶嵌结构的一层或多层之间增强的附着力。镶嵌结构可以通过在衬底顶表面上施加光致抗蚀剂来制造，在在抗蚀剂中产生驻波的条件下曝光光致抗蚀剂，以及显影光致抗蚀剂以提供具有期望的粗糙化或锯齿形轮廓的图案。将图案转移到衬底中，将衬垫施加在衬底底部和侧壁上，并且衬垫填充有导电材料。可以通过在衬底上施加部分衬里材料层，去除部分层的一部分并重复施加和去除步骤来实现粗糙化衬里表面。

30. 发明授权

US06180521B2 Process for manufacturing a contact barrier 失效
标题翻译：制造接触屏障的方法
公开(公告)号：US06180521B2
公开(公告)日：2001-01-30
申请号：US09225598
申请日：1999-01-06
申请人： Patrick W. DeHaven , Anthony G. Domenicucci , Lynne M. Gignac , Glen L. Miles , Prabhat Tiwari , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
发明人： Patrick W. DeHaven , Anthony G. Domenicucci , Lynne M. Gignac , Glen L. Miles , Prabhat Tiwari , Yun-Yu Wang , Horatio S. Wildman , Kwong Hon Wong
IPC分类号： H01L2128
CPC分类号： H01L21/76846 , H01L21/28518 , H01L21/76855 , H01L21/76856 , H01L21/76864
摘要： A process for forming a conductive contact having a flat interface. A layer containing niobium and titanium is deposited on a silicon substrate and the resulting structure is annealed in a nitrogen-containing atmosphere at about 500° C. to about 700° C. By this process, a flatter interface between silicide and silicon, which is less likely to cause junction leakage, is formed on annealing. The step of annealing also produces a more uniform bilayer, which is a better barrier against tungsten encroachment during subsequent tungsten deposition. Larger silicide grains are also formed so that fewer grain boundaries are produced, reducing metal diffusion in grain boundaries. The process can be used to form contacts for very small devices and shallow junctions, such as are required for current and future semiconductor devices.
摘要翻译：一种用于形成具有平坦界面的导电触头的工艺。将含有铌和钛的层沉积在硅衬底上，所得结构在约500℃至约700℃的含氮气氛中退火。通过该过程，硅化物和硅之间的平坦界面是在退火时形成不太可能导致结漏电。退火步骤还产生更均匀的双层，这是在随后的钨沉积期间防止钨侵蚀的更好的屏障。还形成更大的硅化物晶粒，使得产生更少的晶界，减少晶界中的金属扩散。该过程可用于形成非常小的器件和浅结的接触，例如当前和未来的半导体器件所需要的。

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