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21. 发明授权

US06301690B1 Method to improve integrated circuit defect limited yield 有权
标题翻译：提高集成电路缺陷有限产量的方法
公开(公告)号：US06301690B1
公开(公告)日：2001-10-09
申请号：US09294495
申请日：1999-07-12
申请人： Gary S. Ditlow , Daria R. Dooling , David E. Moran , Richard L. Moore , Gustavo E. Tellez , Ralph J. Williams , Thomas W. Wilkins
发明人： Gary S. Ditlow , Daria R. Dooling , David E. Moran , Richard L. Moore , Gustavo E. Tellez , Ralph J. Williams , Thomas W. Wilkins
IPC分类号： G06F1750
CPC分类号： H01L22/20 , H01L23/528 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A method for manufacturing an integrated circuit having improved defect-limited yield. Each conductor on the integrated circuit is represented as an electrical element of a network, having branch voltages and currents. The width of the conductor is advantageously selected to have the minimum width necessary to produce signal levels that have sufficient noise margins. An integrated circuit conductive grid is thus realized having a reduced cross sectional area along a portion of various conductor element lengths, to reduce the risk that particles produced during manufacturing will result in bridging of adjacent conductor elements.
摘要翻译：一种具有改善的缺陷限制产量的集成电路的制造方法。集成电路上的每个导体被表示为具有分支电压和电流的网络的电气元件。有利地，导体的宽度选择为具有产生具有足够噪声容限的信号电平所需的最小宽度。因此，实现了沿着各种导体元件长度的一部分具有减小的横截面面积的集成电路导电栅格，以减少在制造期间产生的颗粒将导致相邻导体元件的桥接的风险。

22. 发明授权

US06189132B1 Design rule correction system and method 失效
标题翻译：设计规则校正系统及方法
公开(公告)号：US06189132B1
公开(公告)日：2001-02-13
申请号：US09057961
申请日：1998-04-09
申请人： Fook-Luen Heng , Zhan Chen , Gustavo E. Tellez , John Cohn , Rani Narayan
发明人： Fook-Luen Heng , Zhan Chen , Gustavo E. Tellez , John Cohn , Rani Narayan
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： A method of modifying a layout of a plurality of objects in accordance with a plurality of predetermined criteria is presented. An objective function is defined for measuring a location perturbation and a separation perturbation of the objects in the layout. A linear system is defined using linear constraints in terms of design rules and the objective function to describe separations between layout objects. The linear system is solved to simultaneously remove violations of the design rules, and shapes and positions of objects in the layout are modified in accordance with the solution of the linear system such that a total perturbation of the objects in the layout is reduced. A system for implementing the present invention is also presented.
摘要翻译：呈现了根据多个预定标准修改多个对象的布局的方法。定义了一个目标函数，用于测量布局中对象的位置扰动和分离扰动。使用线性约束在设计规则和用于描述布局对象之间的分离的目标函数方面定义线性系统。解决线性系统以同时消除违反设计规则的情况，并且根据线性系统的解决方案来修改布局中对象的形状和位置，使得布局中的对象的总扰动减小。还提出了用于实现本发明的系统。

23. 发明申请

US20130268908A1 VIA SELECTION IN INTEGRATED CIRCUIT DESIGN 有权
标题翻译：通过集成电路设计中的选择
公开(公告)号：US20130268908A1
公开(公告)日：2013-10-10
申请号：US13443426
申请日：2012-04-10
申请人： Robert R. Arelt , Jeanne P. S. Bickford , Andrew D. Huber , Gustavo E. Tellez , Karl W. Vinson , Tina Wagner
发明人： Robert R. Arelt , Jeanne P. S. Bickford , Andrew D. Huber , Gustavo E. Tellez , Karl W. Vinson , Tina Wagner
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/12 , Y02P90/265
摘要： Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.
摘要翻译：公开了将通孔有效地实现为多级集成电路布局的解决方案。在各种实施例中，公开了一种创建具有至少一个通孔的多级集成电路布局的方法，所述方法包括：提供多层集成电路布局的至少两层; 以及选择用于连接所述至少两个层的通孔，其中所述选择包括从包括多个通孔类型的通孔库中检索所述通孔，所述多通道类型根据所述通孔库中的每一个的预测制造收益多个通孔。

24. 发明申请

US20110302545A1 DETAILED ROUTABILITY BY CELL PLACEMENT 有权
标题翻译：细节放置的详细的不可靠性
公开(公告)号：US20110302545A1
公开(公告)日：2011-12-08
申请号：US12796501
申请日：2010-06-08
申请人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
发明人： Charles J. Alpert , Andrew D. Huber , Zhuo Li , Gi-Joon Nam , Shyam Ramji , Jarrod A. Roy , Taraneh Taghavi , Gustavo E. Tellez , Paul G. Villarrubia , Natarajan Viswanathan
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A computer implemented method, data processing system, and computer program product for reworking a plurality of cells initially placed in a circuit design. An expander allocates cells to tiles, wherein some tiles have cells. The expander determines a high detailed routing cost tile class, wherein the high detailed routing cost tile class is a class of tiles that are high detailed routing cost tiles. The expander selects a cell within a tile of the high detailed routing cost tile class to form a selected cell and a selected tile. The expander places an expanded bounding box around the selected cell, wherein the bounding box extends to at least one tile adjacent the selected tile. The expander expands the selected cell within the bounding box to form a modified design, determines an aggregate routing cost among other steps, and affirms the modified design for further processing.
摘要翻译：一种计算机实现的方法，数据处理系统和用于重新设计最初放置在电路设计中的多个单元的计算机程序产品。扩展器将单元格分配给图块，其中某些图块具有单元格。扩展器确定高详细路由成本瓦片类，其中高详细路由成本瓦片类是作为高详细路由成本瓦片的瓦片类。扩展器选择高详细路由代价块类别的块内的单元，以形成所选择的单元和所选择的块。扩展器将扩展的边界框放置在所选择的单元周围，其中边界框延伸到与所选择的瓦片相邻的至少一个瓦片。扩展器在边界框内扩展所选单元格以形成修改的设计，确定其他步骤之间的汇总路由成本，并确认修改后的设计以进行进一步处理。

25. 发明授权

US07117456B2 Circuit area minimization using scaling 失效
标题翻译：电路面积缩小使用缩放
公开(公告)号：US07117456B2
公开(公告)日：2006-10-03
申请号：US10707287
申请日：2003-12-03
申请人： Michael S. Gray , Kevin W. McCullen , Gustavo E. Tellez , Robert F. Walker
发明人： Michael S. Gray , Kevin W. McCullen , Gustavo E. Tellez , Robert F. Walker
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5068
摘要： A method, system and program product that implements area minimization of a circuit design while respecting the explicit and implicit design constraints, in the form of ground rules and user intent. A longest path algorithm is used to generate a scaling factor. The scaling factor is used to reduce the size of the circuit design to the minimum legal size. The scaling may be followed by application of minpert analysis to correct any errors introduced by the scaling. The resulting design is shrunk (or expanded) with all elements shrinking (or growing) together by the same factor, and with the relative relationships of elements maintained. In addition, the invention is operational in the presence of a positive cycle, can be run with scaling that freezes the sizes of any structure or ground rule, and can be applied to technology migration.
摘要翻译：一种方法，系统和程序产品，其以基本规则和用户意图的形式实现电路设计的区域最小化，同时遵守显式和隐式设计约束。最长路径算法用于生成比例因子。缩放因子用于将电路设计的尺寸减小到最小法律尺寸。缩放可能之后是应用minpert分析来校正由缩放引入的任何错误。所产生的设计缩小（或扩展），所有元素都通过相同的因素一起缩减（或增长），并保持元素的相对关系。此外，本发明在存在正循环的情况下是可操作的，可以用缩放来运行，其结冰或冻结规则的尺寸，并且可以应用于技术迁移。

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