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21. 发明授权

US5955898A Selector and decision wait using pass gate XOR 失效
标题翻译：选择器和决定等待使用传输门XOR
公开(公告)号：US5955898A
公开(公告)日：1999-09-21
申请号：US885169
申请日：1997-06-30
申请人： Ivan E. Sutherland , William S. Coates , Jon K. Lexau
发明人： Ivan E. Sutherland , William S. Coates , Jon K. Lexau
IPC分类号： H03K17/693 , H03K19/0948
CPC分类号： H03K17/693
摘要： A logic gate includes a plurality of pass gates forming a double rail pass gate XOR or reversing switch providing the same functionality as a conventional XOR gate. Consequently, the pass gate XOR can substitute for XOR gates in circuits such as a selector circuit and decision wait circuit, but with faster responses and fewer transistors than the conventional XOR gate. Each pass gate includes a P-type and an N-type transistor coupled in parallel. A control input and its complement are coupled to the gates of the transistors to selectively pass signals at the input of the pass gate to its output.
摘要翻译：逻辑门包括形成双轨栅极XOR或反向开关的多个栅极，提供与传统XOR栅极相同的功能。因此，通过门XOR可以在诸如选择器电路和判决等待电路的电路中替代XOR门，但是具有比常规XOR门更快的响应和更少的晶体管。每个通过门包括并联耦合的P型和N型晶体管。控制输入及其补码耦合到晶体管的栅极，以选择性地将通孔的输入端处的信号传递到其输出端。

22. 发明申请

US20090086793A1 REPEATER CIRCUIT 有权
标题翻译：重复电路
公开(公告)号：US20090086793A1
公开(公告)日：2009-04-02
申请号：US11863368
申请日：2007-09-28
申请人： Scott M. Fairbanks , William S. Coates
发明人： Scott M. Fairbanks , William S. Coates
IPC分类号： H04B3/36
CPC分类号： H04B3/36
摘要： A repeater circuit configured to duplicate or otherwise coordinate signal transitions between state conductors, such as for use in asynchronous communication systems. The repeater circuit may include a state node or other feature to facilitate enforcing or otherwise ordering transitioning of the state conductors.
摘要翻译：中继器电路被配置为复制或以其他方式协调状态导体之间的信号转换，例如用于异步通信系统。中继器电路可以包括状态节点或其他特征以便于强制或以其他方式命令状态导体的转换。

23. 发明授权

US06741616B1 Switch fabric for asynchronously transferring data within a circuit 有权
标题翻译：交换结构，用于在电路内异步传输数据
公开(公告)号：US06741616B1
公开(公告)日：2004-05-25
申请号：US09685009
申请日：2000-10-05
申请人： Ivan E. Sutherland , William S. Coates , Ian W. Jones
发明人： Ivan E. Sutherland , William S. Coates , Ian W. Jones
IPC分类号： H04J304
CPC分类号： H04L12/4625 , H04L49/101
摘要： One embodiment of the present invention provides a system that facilitates asynchronously routing data within a circuit. This system includes a data destination horn, for routing data from a trunk line to a plurality of destinations. This data destination horn includes a plurality of one-to-many switching elements organized into a tree of at least one level that fans out from the trunk line to the plurality of destinations. It also includes a plurality of memory elements for storing data in transit between the plurality of one-to-many switching elements. An asynchronous control structure is coupled to the data destination horn, and is configured to control the propagation of data through the data destination horn, so that when a given data item appears at an input of a memory element, the given data item is asynchronously latched into the memory element as soon space becomes available in the memory element without having to wait for a clock signal. One embodiment of the present invention additionally includes a data source funnel, for routing data from a plurality of sources into the trunk line. This data source funnel includes a plurality of many-to-one switching elements organized into a tree of at least one level that fans in from the plurality of sources to into the trunk line. It also includes a plurality of funnel memory elements for storing data in transit between the plurality of many-to-one switching elements. Moreover, the asynchronous control structure is additionally configured to control propagation of data through the data source funnel.
摘要翻译：本发明的一个实施例提供一种便于在电路内异步路由数据的系统。该系统包括数据目的地喇叭，用于将数据从中继线路由到多个目的地。该数据目的地喇叭包括组合成至少一个级别的树的多个一对多交换元件，其从干线到多个目的地扇出。它还包括用于存储在多个一对多交换元件之间传输的数据的多个存储元件。异步控制结构被耦合到数据目标喇叭，并且被配置为控制数据通过数据目的地喇叭的传播，使得当给定的数据项出现在存储器元件的输入端时，给定的数据项被异步锁存随着空间在存储器元件中可用，而不必等待时钟信号，就进入存储元件。本发明的一个实施例还包括数据源漏斗，用于将数据从多个源路由到干线。该数据源漏斗包括多个多对一的开关元件，其组织成至少一个级别的树，该多个级别的风扇从多个源中进入干线。它还包括多个漏斗存储器元件，用于存储在多个多对一开关元件之间的传输中的数据。此外，异步控制结构还被配置为控制数据通过数据源漏斗的传播。

24. 发明授权

US06360288B1 Method and modules for control of pipelines carrying data using pipelines carrying control signals 失效
标题翻译：使用承载控制信号的管道控制承载数据的管道的方法和模块
公开(公告)号：US06360288B1
公开(公告)日：2002-03-19
申请号：US08953767
申请日：1997-10-17
申请人： Ivan E. Sutherland , William S. Coates , Charles E. Molnar , Robert F. Sproull
发明人： Ivan E. Sutherland , William S. Coates , Charles E. Molnar , Robert F. Sproull
IPC分类号： G06F1300
CPC分类号： G06F9/3869 , G06F9/3867
摘要： A computer system is described in which control of the flow of data items in one pipeline is achieved using the values of control elements in another pipeline. Typically, each pipeline includes elements known as “places” and “paths,” and the pipelines have special connections between them by which the data present in a place in a first pipeline can be used to control the disposition of data in the second pipeline. For example, the first pipeline can control the second pipeline to enable the addition, deletion, or steering of data items in the second pipeline.
摘要翻译：描述了一种计算机系统，其中使用另一流水线中的控制元件的值来实现一条流水线中的数据项流的控制。通常，每个管道包括被称为“地点”和“路径”的元件，并且管道在它们之间具有特殊的连接，通过该特殊连接，可以使用存在于第一管道中的位置的数据来控制第二管道中的数据的布置。例如，第一流水线可以控制第二流水线，以允许第二流水线中的数据项的添加，删除或转向。

25. 发明授权

US06169422A Apparatus and methods for high throughput self-timed domino circuits 失效
标题翻译：用于高通量自定时多米诺骨牌电路的装置和方法
公开(公告)号：US06169422A
公开(公告)日：2001-01-02
申请号：US09119032
申请日：1998-07-20
申请人： David L. Harris , William S. Coates
发明人： David L. Harris , William S. Coates
IPC分类号： H03K19096
CPC分类号： H03K19/0963
摘要： Asynchronous circuitry provides a domino circuit having short cycle times and zero overhead latency. The control circuit of a datapath circuit may utilize a completion signal from the datapath circuit to develop a request signal to the datapath circuit. The request signal may also be based on a request signal from a previous stage. Using the completion signal of a stage to develop the request signal for the same stage allows the circuitry to reduce the impact of constraints that are required for the asynchronous circuitry to operate. Similarly, using the request signal from a previous stage of the asynchronous circuitry to develop the request signal for a present stage also allows the circuitry to reduce the impact of constraints required to implement the asynchronous circuitry. These techniques allow the achievement of fast cycle times while maintaining zero overhead.
摘要翻译：异步电路提供具有短周期时间和零开销延迟的多米诺骨牌电路。数据路径电路的控制电路可以利用来自数据路径电路的完成信号来产生对数据路径电路的请求信号。请求信号也可以基于来自前一级的请求信号。使用级的完成信号来开发用于相同级的请求信号，使得电路可以减少异步电路运行所需的约束的影响。类似地，使用来自异步电路的前一级的请求信号来开发用于当前级的请求信号也允许电路减少实现异步电路所需的约束的影响。这些技术允许实现快速循环时间，同时保持零开销。

26. 发明授权

US6085316A Layered counterflow pipeline processor with anticipatory control 失效
标题翻译：具有预期控制的分层逆流管线处理器
公开(公告)号：US6085316A
公开(公告)日：2000-07-04
申请号：US123587
申请日：1998-07-28
申请人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
发明人： Ivan E. Sutherland , Charles E. Molnar, deceased , Ian W. Jones , William S. Coates , Jon Lexau
IPC分类号： G06F9/38 , G06F15/78 , G06F15/80 , G06F9/28 , G06F13/40
CPC分类号： G06F9/3873 , G06F15/8007 , G06F15/8053 , G06F9/3867
摘要： A layered counterflow pipeline structure is described in which sub-tasks performed at each stage in a counterflow pipeline processor are separated into different layers. As words flow through the counterflow pipeline processor, they are divided into partial words which are supplied to the different layers, GET, CHECK and PROCESS, for appropriate handling by that portion of each stage. In the GET layer, partial words passing through each stage are analyzed to determine whether they constitute an encounter pair. In the CHECK layer a determination is made as to whether the word selected by the GET layer requires further modification. Finally, in the PROCESS layer operations are performed on the words themselves based upon control messages from the other layers. The layers of the processor communicate with each other using suitable communication paths such as First In First Out registers.
摘要翻译：描述了分层逆流管线结构，其中在逆流管线处理器中的每个阶段执行的子任务被分成不同的层。当文字流过逆流流水线处理器时，它们被分成供应给不同层的部分单词，GET，CHECK和PROCESS，以便每个阶段的该部分进行适当的处理。在GET层中，分析通过每个阶段的部分单词，以确定它们是否构成遇到对。在CHECK层中，确定由GET层选择的单词是否需要进一步修改。最后，在PROCESS层中，基于来自其他层的控制消息对单词本身执行操作。处理器的层使用诸如先进先出寄存器之类的合适的通信路径彼此通信。

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