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21. 发明授权

US07131024B1 Multiple transmit data rates in programmable logic device serial interface 有权
标题翻译：可编程逻辑器件串行接口中的多个传输数据速率
公开(公告)号：US07131024B1
公开(公告)日：2006-10-31
申请号：US10670813
申请日：2003-09-24
申请人： Ramanand Venkata , Chong H Lee , Rakesh Patel
发明人： Ramanand Venkata , Chong H Lee , Rakesh Patel
IPC分类号： G06F1/06
CPC分类号： G06F1/06
摘要： A serial interface for a programmable logic device provides multiple data rates in different channels by generating a central serial clock and providing at least one divider in each channel that can divide the central clock by different integer values. For additional variation in clock rate, two or more different central clocks can be provided, with each channel then being able to divide any of the central clocks to provide the desired local clock. Lower speed parallel clocks can be generated locally by further dividing the divided serial clock. Alternatively, the central serial clock or clocks may be divided centrally to provide a central parallel clock or clocks which can then be used locally as a local parallel clock.
摘要翻译：用于可编程逻辑器件的串行接口通过产生中央串行时钟来在不同的通道中提供多个数据速率，并且在每个通道中提供至少一个可以将中心时钟除以不同整数值的分频器。对于时钟速率的额外变化，可以提供两个或多个不同的中央时钟，每个信道然后能够分割任何中央时钟以提供期望的本地时钟。可以通过进一步分割串行时钟来本地生成低速并行时钟。或者，中央串行时钟可以集中分配以提供中央并行时钟或时钟，然后可以将其本地地用作本地并行时钟。

22. 发明授权

US07659838B2 Deserializer circuitry for high-speed serial data receivers on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据接收器的解串器电路
公开(公告)号：US07659838B2
公开(公告)日：2010-02-09
申请号：US11359273
申请日：2006-02-21
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Tim Tri Hoang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03M9/00
摘要： Deserializer circuitry for high-speed serial data receiver circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting serial data to parallel data having any of several data widths. The circuitry can also operate at any frequency in a wide range of frequencies. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据接收器电路的解串器电路包括用于将串行数据转换成具有若干数据宽度的并行数据的电路。电路也可以在宽频率范围内的任何频率下工作。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

23. 发明申请

US20110068845A1 SERIALIZER CIRCUITRY FOR HIGH-SPEED SERIAL DATA TRANSMITTERS ON PROGRAMMABLE LOGIC DEVICE INTEGRATED CIRCUITS 有权
标题翻译：用于可编程逻辑器件集成电路的高速串行数据传输器的串行电路
公开(公告)号：US20110068845A1
公开(公告)日：2011-03-24
申请号：US12953766
申请日：2010-11-24
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch ZaIiznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch ZaIiznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： G06F1/04 , H03K3/01
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

24. 发明授权

US07292070B1 Programmable PPM detector 有权
标题翻译：可编程PPM探测器
公开(公告)号：US07292070B1
公开(公告)日：2007-11-06
申请号：US11200579
申请日：2005-08-09
申请人： Seungmyon Park , Ramanand Venkata , Chong Lee
发明人： Seungmyon Park , Ramanand Venkata , Chong Lee
IPC分类号： G01R23/02 , H03D3/00 , H03K9/06
CPC分类号： H03K19/1774 , H03K19/17744
摘要： A device such as a programmable logic device (“PLD”) includes circuitry for detecting the PPM frequency difference between two input clock signals. For example, this circuitry may accept a user-programmable PPM threshold value and output a signal when this threshold value is met.
摘要翻译：诸如可编程逻辑器件（“PLD”）的器件包括用于检测两个输入时钟信号之间的PPM频差的电路。例如，该电路可以接受用户可编程的PPM阈值，并且当满足该阈值时输出信号。

25. 发明授权

US08570197B2 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US08570197B2
公开(公告)日：2013-10-29
申请号：US12953766
申请日：2010-11-24
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

26. 发明授权

US07656187B2 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US07656187B2
公开(公告)日：2010-02-02
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Yuryevich Shumarayev , Tim Tri Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H03K19/173
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以便于诸如电路设计和验证之类的事情。

27. 发明授权

US07366267B1 Clock data recovery with double edge clocking based phase detector and serializer/deserializer 有权
标题翻译：基于双边沿时钟的相位检测器和串行器/解串器的时钟数据恢复
公开(公告)号：US07366267B1
公开(公告)日：2008-04-29
申请号：US10059014
申请日：2002-01-29
申请人： Chong Lee , Ramanand Venkata
发明人： Chong Lee , Ramanand Venkata
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , H03K5/135 , H03M9/00 , H04L7/0337
摘要： A programmable logic device (“PLD”) is augmented with programmable clock data recover (“CDR”) circuitry to allow the PLD to communicate via any of a large number of CDR signaling protocols. The CDR circuitry may be integrated with the PLD, or it may be wholly or partly on a separate integrated circuit. The circuitry may be capable of CDR input, CDR output, or both. The CDR capability may be provided in combination with other non-CDR signaling capability such as non-CDR low voltage differential signaling (“LVDS”). THE CDR circuitry is provided with a programmable serializer and/or deserializer that can support higher data clock rates than the highest clock rate associated with the reference clock signal or clock signal from a phase locked loop circuit.
摘要翻译：可编程逻辑器件（“PLD”）用可编程时钟数据恢复（“CDR”）电路进行增强，以允许PLD通过大量CDR信令协议中的任何一个进行通信。 CDR电路可以与PLD集成，或者它可以全部或部分地在单独的集成电路上。电路可能能够进行CDR输入，CDR输出或两者。 CDR能力可以与其他非CDR信令能力组合提供，例如非CDR低电压差分信号（“LVDS”）。 CDR电路配备有可编程串行器和/或解串器，其可以支持比与来自锁相环电路的参考时钟信号或时钟信号相关联的最高时钟速率更高的数据时钟速率。

28. 发明申请

US20070030184A1 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US20070030184A1
公开(公告)日：2007-02-08
申请号：US11364589
申请日：2006-02-27
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H03M9/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

29. 发明授权

US07848318B2 Serializer circuitry for high-speed serial data transmitters on programmable logic device integrated circuits 有权
标题翻译：用于可编程逻辑器件集成电路上的高速串行数据发射器的串行器电路
公开(公告)号：US07848318B2
公开(公告)日：2010-12-07
申请号：US11364589
申请日：2006-02-27
申请人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
发明人： Toan Thanh Nguyen , Thungoc Tran , Sergey Yuryevich Shumarayev , Arch Zaliznyak , Shoujun Wang , Ramanand Venkata , Chong Lee
IPC分类号： H04Q11/00
CPC分类号： H03K19/00 , H03K19/17744 , H03M9/00 , H04L1/243 , H04L7/0008 , H04L7/033 , H04L25/0266
摘要： Serializer circuitry for high-speed serial data transmitter circuitry on a programmable logic device (“PLD”) or the like includes circuitry for converting parallel data having any of several data widths to serial data. The circuitry can also operate at any frequency in a wide range of frequencies, and can make use of reference clock signals having any of several relationships to the parallel data rate and/or the serial data rate. The circuitry is configurable/re-configurable in various respects, at least some of which configuration/re-configuration can be dynamically controlled (i.e., during user-mode operation of the PLD).
摘要翻译：用于可编程逻辑器件（“PLD”）等上的高速串行数据发射器电路的串行器电路包括用于将具有若干数据宽度中的任一个的并行数据转换为串行数据的电路。电路还可以在宽频率范围内的任何频率下操作，并且可以利用具有与并行数据速率和/或串行数据速率的几个关系中的任何一个的参考时钟信号。该电路在各个方面是可配置的/可重新配置的，其中至少一些配置/重新配置可被动态地控制（即在PLD的用户模式操作期间）。

30. 发明申请

US20070058618A1 Multi-channel communication circuitry for programmable logic device integrated circuits and the like 有权
标题翻译：用于可编程逻辑器件集成电路等的多通道通信电路
公开(公告)号：US20070058618A1
公开(公告)日：2007-03-15
申请号：US11288810
申请日：2005-11-28
申请人： Thungoc Tran , Sergey Shumarayev , Tim Hoang , Ning Xue , Chong Lee , Ramanand Venkata
发明人： Thungoc Tran , Sergey Shumarayev , Tim Hoang , Ning Xue , Chong Lee , Ramanand Venkata
IPC分类号： H04L12/50
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An integrated circuit like a programmable logic device (“PLD”) includes multiple channels of data communication circuitry. Circuitry is provided for selectively sharing signals (e.g., control-type signals) among these channels in groupings of various size so that the device can better support communication protocols that require various numbers of channels (e.g., one channel operating relatively independently, four channels working together, eight channels working together, etc.). The signals shared may include a clock signal, a FIFO write enable signal, a FIFO read enable signal, or the like. The circuit arrangements are preferably modular (i.e., the same or substantially the same from one channel to the next and/or from one group of channels to the next) to facilitate such things as circuit design and verification.
摘要翻译：诸如可编程逻辑器件（“PLD”）的集成电路包括多个通道的数据通信电路。提供电路用于在各种尺寸的分组中选择性地共享这些信道中的信号（例如，控制型信号），使得设备可以更好地支持需要各种信道数量的通信协议（例如，一个信道相对独立地操作，四个信道工作一起，八个渠道在一起等）。共享的信号可以包括时钟信号，FIFO写使能信号，FIFO读使能信号等。电路布置优选地是模块化的（即，从一个通道到下一个通道和/或从一组通道到下一个通道相同或基本相同），以促进诸如电路设计和验证的事情。

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