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21. 发明授权

US06399445B1 Fabrication technique for controlled incorporation of nitrogen in gate dielectric 有权
标题翻译：在栅极电介质中控制氮的结合的制造技术
公开(公告)号：US06399445B1
公开(公告)日：2002-06-04
申请号：US09212508
申请日：1998-12-15
申请人： Sunil V. Hattangady , Srikanth Krishnan , Robert Kraft
发明人： Sunil V. Hattangady , Srikanth Krishnan , Robert Kraft
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/3144 , H01L21/3215 , H01L29/513 , H01L29/518
摘要： A method of fabricating a semiconductor MOS device and the device wherein there is initially provided a semiconductor substrate having a gate insulator layer thereon and intimate therewith. A region of one of a nitride or oxynitride is formed at the surface region of the layer remote from the substrate having sufficient nitride to act as a barrier against the migration of dopant therethrough to the substrate. A doped polysilicon gate or a metal gate is then formed over the region of a nitride or oxynitride. The amount of nitride in the insulator layer intimate and closely adjacent to the substrate is insufficient to materially alter the characteristics of the device being fabricated. The substrate is preferably silicon, the oxide and nitride are preferably those of silicon and the dopant preferably includes boron. The step of forming a region of one of a nitride or oxynitride includes the step of injecting neutral atomic nitrogen into the surface of the gate insulator layer surface remote from the substrate. The region of one of a nitride or oxynitride is from about 1 to about 2 monolayers.
摘要翻译：一种制造半导体MOS器件的方法及其装置，其中最初提供了一种半导体衬底，其上具有栅极绝缘体层并且具有密封性。氮化物或氮氧化物之一的区域形成在远离具有足够氮化物的衬底的层的表面区域上，以作为防止掺杂剂向衬底迁移的阻挡层。然后在氮化物或氮氧化物的区域上形成掺杂的多晶硅栅极或金属栅极。绝缘体层中与衬底紧密并紧密相邻的氮化物的量不足以实质上改变正在制造的器件的特性。衬底优选为硅，氧化物和氮化物优选为硅，掺杂剂优选包括硼。形成氮化物或氮氧化物之一的区域的步骤包括将中性原子氮注入远离衬底的栅极绝缘体层表面的步骤。氮化物或氧氮化物之一的区域为约1至约2个单层。

22. 发明授权

US5796151A Semiconductor stack having a dielectric sidewall for prevention of oxidation of tungsten in tungsten capped poly-silicon gate electrodes 失效
标题翻译：具有用于防止钨封端的多晶硅栅电极中钨的氧化的电介质侧壁的半导体叠层
公开(公告)号：US5796151A
公开(公告)日：1998-08-18
申请号：US770019
申请日：1996-12-19
申请人： Wei-Yung Hsu , Dirk N. Anderson , Robert Kraft
发明人： Wei-Yung Hsu , Dirk N. Anderson , Robert Kraft
IPC分类号： H01L29/78 , H01L21/28 , H01L21/285 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/49 , H01L29/76 , H01L23/58 , H01L29/94 , H01L31/62
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28114 , H01L21/28167 , H01L21/28512 , H01L29/4941 , H01L29/66575
摘要： In an integrated circuit, gate electrode stack of which is subjected to self-alignment processes, the sheet resistance is lowered by including a tungsten layer 15. The tungsten layer 14 is protected by a sidewall material 21 of SiN.sub.x or SiO.sub.2 after an etching step which did not extend to the substrate 11. During a subsequent etching step in which the stack extends to the substrate 11, the sidewall material 31 acts as a hard mask protecting the upper portion of the stack. After the lower portion of the stack is protected by a re-oxidation layer 41, the entire stack can be processed further without deterioration of the sheet resistance of the tungsten layer 15.
摘要翻译：在其栅极电极堆叠进行自对准处理的集成电路中，通过包括钨层15来降低薄层电阻。在蚀刻步骤之后，钨层14被SiN x或SiO 2的侧壁材料21保护，没有延伸到基板11.在其中堆叠延伸到基板11的随后的蚀刻步骤中，侧壁材料31用作保护堆叠的上部的硬掩模。在堆叠的下部被再氧化层41保护之后，可以进一步处理整个堆叠而不会降低钨层15的薄层电阻。

23. 发明授权

US4894838A Electron beam preionization of a high pressure self-sustaining gas laser 失效
标题翻译：高压自持气体激光器的电子束预电离
公开(公告)号：US4894838A
公开(公告)日：1990-01-16
申请号：US259687
申请日：1988-10-19
申请人： Robert Kraft , Victor H. Hasson
发明人： Robert Kraft , Victor H. Hasson
IPC分类号： H01S3/0971
CPC分类号： H01S3/09716
摘要： A high pressure self-sustained gas laser operating at a high specific energy loading and long pulselength. The laser comprises an endless duct for circulating a laser generating gaseous medium and two discharge electrodes for exciting the molecules of the gaseous medium. Behind the discharge cathode electrode is an electron-beam transmitter for transmitting a beam of preionizing electrons into the gaseous medium to preionize the region near the cathode discharge electrode. The region unpreionized by the electron beam is ionized by drifting electrons from the cathode region and avalanche ionization. The applied discharge voltage never exceeds the glow voltage allowing low discharge flush factors under repetitive operation with flowing laser gas.
摘要翻译：高压自持式气体激光器以高比能量负载和长脉冲长度运行。激光器包括用于使产生气体介质的激光循环的环形管道和用于激发气体介质分子的两个放电电极。放电阴极电极后面是一个电子束发射器，用于将预电离的电子束传输到气体介质中，以便使阴极放电电极附近的区域发生离子化。由电子束未被去除的区域通过从阴极区域漂移电子和雪崩电离而离子化。施加的放电电压不会超过辉光电压，允许在重复操作下使用流动的激光气体的低放电冲洗因子。

24. 发明申请

US20130210062A1 In Vitro Cellular Bioassay for Neurotoxicity Testing 有权
标题翻译：体外细胞生物测定用于神经毒性测试
公开(公告)号：US20130210062A1
公开(公告)日：2013-08-15
申请号：US13639541
申请日：2011-04-08
申请人： Linda L. Restifo , Robert Kraft
发明人： Linda L. Restifo , Robert Kraft
IPC分类号： C12Q1/02
CPC分类号： C12Q1/025 , G01N33/5058
摘要： The present invention provides neurotoxicity and developmental neurotoxicity screening methods employing primary cultured neurons from Drosophila.
摘要翻译：本发明提供了使用来自果蝇的原代培养神经元的神经毒性和发育性神经毒性筛选方法。

25. 发明申请

US20080014739A1 Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability 审中-公开
标题翻译：氮化硅/氧掺杂碳化硅蚀刻停止双层以提高互连可靠性
公开(公告)号：US20080014739A1
公开(公告)日：2008-01-17
申请号：US11475924
申请日：2006-06-28
申请人： Laura M. Matz , Asad Haider , Robert Kraft
发明人： Laura M. Matz , Asad Haider , Robert Kraft
IPC分类号： H01L21/4763 , H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L23/53295 , H01L21/76832 , H01L21/76834 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In accordance with the invention, there are semiconductor devices and methods for making semiconductor devices and film stacks in an integrated circuits. The method of making a semiconductor device can comprise forming a semiconductor structure comprising at least one copper interconnect, forming an etch stop bi-layer comprising a first layer and a second layer, wherein the first layer comprising silicon nitride is disposed over the semiconductor structure comprising at least one copper interconnect, and the second layer comprising silicon oxy-carbide is disposed over the first layer, and depositing a dielectric layer over the etch stop bi-layer.
摘要翻译：根据本发明，存在用于在集成电路中制造半导体器件和薄膜叠层的半导体器件和方法。制造半导体器件的方法可以包括形成包括至少一个铜互连的半导体结构，形成包括第一层和第二层的蚀刻停止双层，其中包含氮化硅的第一层设置在半导体结构之上，包括至少一个铜互连，并且包含碳化硅碳的第二层设置在第一层之上，并且在蚀刻停止双层上沉积介电层。

26. 发明申请

US20070298521A1 METHOD FOR CLEANING POST-ETCH NOBLE METAL RESIDUES 有权
标题翻译：清除后处理金属残留物的方法
公开(公告)号：US20070298521A1
公开(公告)日：2007-12-27
申请号：US11669759
申请日：2007-01-31
申请人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
发明人： Yaw S. Obeng , Kezhakkedath R. Udayakumar , Scott Robert Summerfelt , Sanjeev Aggarwal , Francis Gabriel Celii , Lindsey H. Hall , Robert Kraft , Theodore S. Moise
IPC分类号： H01L21/00
CPC分类号： H01L21/02071 , H01L21/02129 , H01L21/02164 , H01L21/0217 , H01L21/02175 , H01L21/022 , H01L21/02263 , H01L21/31683 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.
摘要翻译：提出了制造半导体器件的方法。一方面，该方法包括在半导体衬底上形成导电和铁电材料层。图案化材料层以形成铁电电容器的电极和铁电层，其中在铁电电容器的侧壁上产生导电的含贵金属的聚合物。该方法还包括将含导电贵金属的聚合物转化为非导电金属氧化物。转化包括从含导电贵金属的聚合物形成水溶性金属盐，并使水溶性金属盐与酸性水溶液反应，形成金属氢氧化物。转化还包括氧化金属氢氧化物以形成非导电金属氧化物。

27. 发明申请

US20110205140A1 VARIABLE PITCH MANDREL WOUND ANTENNAS AND SYSTEMS AND METHODS OF MAKING SAME 失效
标题翻译：可变的人造天线和系统及其制造方法
公开(公告)号：US20110205140A1
公开(公告)日：2011-08-25
申请号：US12950636
申请日：2010-11-19
申请人： Paul Amadeo , Jose Flores , Robert Kraft
发明人： Paul Amadeo , Jose Flores , Robert Kraft
IPC分类号： H01Q7/00 , H01P11/00
CPC分类号： H01Q7/00 , G06K19/07779 , G06K19/07781 , H01F41/074 , H01F41/098 , H01Q1/2225 , Y10T29/49016
摘要： A system and method for fabricating a mandrel wound antenna are provided. The method includes securing a first end of a wire to a first portion of a mandrel tool, where the mandrel tool includes a faceplate supporting a plurality of posts, and the posts arranged and disposed to define non-overlapping circumferential patterns. The method also includes wrapping the wire around outer peripheries of the plurality of posts to form non-overlapping wire coils around the plurality of circumferential patterns to provide an antenna. The method further includes securing a second end of the wire to a second portion of the mandrel tool, cutting the wire in proximity to the second end, attaching the antenna to a substrate separate from the faceplate, and detaching the antenna from the faceplate.
摘要翻译：提供了一种用于制造心轴缠绕天线的系统和方法。该方法包括将线的第一端固定到心轴工具的第一部分，其中心轴工具包括支撑多个柱的面板，以及布置和设置以限定非重叠圆周图案的柱。该方法还包括围绕多个柱的外周缠绕线以在多个圆周图案周围形成不重叠的线圈以提供天线。该方法还包括将线的第二端固定到心轴工具的第二部分，将线接近第二端切割，将天线连接到与面板分离的基底，以及将天线从面板上分离。

28. 发明授权

US07687407B2 Method for reducing line edge roughness for conductive features 有权
标题翻译：降低导线特征线边缘粗糙度的方法
公开(公告)号：US07687407B2
公开(公告)日：2010-03-30
申请号：US11070593
申请日：2005-03-02
申请人： David G. Farber , Brian E. Goodllin , Robert Kraft
发明人： David G. Farber , Brian E. Goodllin , Robert Kraft
IPC分类号： H01L21/302
CPC分类号： H01L21/31116 , H01L21/76804 , H01L21/76816
摘要： The present invention provides an interconnect structure, a method of manufacture therefore, and a method for manufacturing an integrated circuit including the same. The method for forming the interconnect structure, among other steps, includes subjecting a first portion (510) of a substrate (220) to a first etch process, the first etch process designed to etch at a first entry angle (θ1), and subjecting a second portion (610) of the substrate (220) to a second different etch process, the second different etch process designed to etch at a second lesser entry angle (θ2).
摘要翻译：本发明提供一种互连结构，因此制造方法，以及一种用于制造包括该互连结构的集成电路的方法。用于形成互连结构的方法以及其他步骤包括使衬底（220）的第一部分（510）经受第一蚀刻工艺，第一蚀刻工艺被设计为以第一入射角（θ; 1）蚀刻，以及对所述衬底（220）的第二部分（610）进行第二不同蚀刻工艺，所述第二不同蚀刻工艺被设计成以第二较小入射角（θ; 2）蚀刻。

29. 发明授权

US07119006B2 Via formation for damascene metal conductors in an integrated circuit 有权
标题翻译：集成电路中镶嵌金属导体的通孔形成
公开(公告)号：US07119006B2
公开(公告)日：2006-10-10
申请号：US10304943
申请日：2002-11-26
申请人： Robert Kraft
发明人： Robert Kraft
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/76813
摘要： A method of fabricating an integrated circuit, having copper metallization formed by a dual damascene process, is disclosed. A layered insulator structure is formed over a first conductor (22), within which a second conductor (40) is formed to contact the first conductor. The layered insulator structure includes a via etch stop layer (24), an interlevel dielectric layer (26), a trench etch stop layer (28), an intermetal dielectric layer (30), and a hardmask layer (32). The interlevel dielectric layer (26) and the intermetal dielectric layer (30) are preferably of the same material. A via is partially etched through the intermetal dielectric layer (30), and through an optional trench etch stop layer (28). A trench location is then defined by photoresist (38), and this trench location is transferred to the hardmask layer (32). Simultaneous etching of the trench through intermetal dielectric layer (30), stopping on the trench etch stop layer (28) if present, simultaneously with the etching of the remainder of the via through the interlevel dielectric layer (26) that stops on the via etch stop layer (24), is then performed. After clearing the via etch stop layer (24) from the via bottom, a copper conductor (40) is then formed into the trench and via, for example by electroplating and planarization by chemical mechanical polishing over a barrier layer (41).
摘要翻译：公开了一种制造具有通过双镶嵌工艺形成的铜金属化的集成电路的方法。在第一导体（22）上形成分层绝缘体结构，其中第二导体（40）形成为与第一导体接触。分层绝缘体结构包括通孔蚀刻停止层（24），层间介电层（26），沟槽蚀刻停止层（28），金属间介质层（30）和硬掩模层（32）。层间电介质层（26）和金属间电介质层（30）优选为相同的材料。通过金属间介质层（30）部分地蚀刻通孔，并通过可选的沟槽蚀刻停止层（28）蚀刻。然后由光致抗蚀剂（38）限定沟槽位置，并且该沟槽位置被转移到硬掩模层（32）。通过金属间电介质层（30）同时蚀刻沟槽，停止在沟槽蚀刻停止层（28）上，如果存在的话，同时蚀刻通过在通孔蚀刻上停止的层间介质层（26）的通孔的其余部分停止层（24）。在从通孔底部清除通孔蚀刻停止层（24）之后，铜导体（40）然后例如通过在阻挡层（41）上的化学机械抛光进行电镀和平坦化而形成沟槽和通孔。

30. 发明申请

US20060096295A1 Methods for operating gas turbine engines 有权
公开(公告)号：US20060096295A1
公开(公告)日：2006-05-11
申请号：US11312058
申请日：2005-12-20
申请人： Robert Kraft
发明人： Robert Kraft
IPC分类号： F02C5/00
CPC分类号： F23C15/00 , F02C5/10 , F05D2260/96 , F05D2270/14 , F23R7/00 , Y02T50/671
摘要： A method for operating a pulse detonation system. The method includes providing a pulse detonation chamber including a plurality of detonation tubes extending therein, and detonating a mixture of fuel and air within each detonation tube such that at least a first tube is detonated at a different time than at least a second detonation tube.

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