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21. 发明授权

US07791601B2 Efficient object storage for zone rendering 有权
标题翻译：用于区域渲染的高效对象存储
公开(公告)号：US07791601B2
公开(公告)日：2010-09-07
申请号：US11897738
申请日：2007-08-31
申请人： Peter L. Doyle
发明人： Peter L. Doyle
IPC分类号： G06T17/00 , G06T15/30 , G06T15/10
CPC分类号： G06T15/005
摘要： Similar, contiguous primitives are stored as a single primitive in zone rendering bins. A primitive packet used in the bin is allowed to vary in length and the currently open type of primitive is recorded on a per-bin basis. A special code is used to specify a variable number of subsequent indices. With this mechanism, the hardware is able to start outputting and replicating primitive commands into bin lists on the fly without requiring the buffering of the entire primitive. Given the variable nature of the primitive instruction, multiple similar/sequential primitives can be concatenated using a single primitive command header.
摘要翻译：类似的连续原语作为单个基元存储在区域渲染区域中。允许在箱中使用的原始包在长度上变化，并且当前打开的原语类型以每个箱为单位被记录。特殊代码用于指定可变数量的后续索引。利用这种机制，硬件能够在不需要缓冲整个原语的情况下开始将原始命令输出和复制到bin列表中。给定基本指令的可变性质，可以使用单个基元命令头连接多个相似/顺序图元。

22. 发明授权

US06882349B2 Efficient image allocation for zone rendering 失效
标题翻译：区域渲染的高效图像分配
公开(公告)号：US06882349B2
公开(公告)日：2005-04-19
申请号：US10038787
申请日：2001-12-31
申请人： Peter L. Doyle
发明人： Peter L. Doyle
IPC分类号： G06T15/00 , G06T15/40 , G09G5/00
CPC分类号： G06T15/005 , G06T15/40
摘要： Embodiments of the present invention efficiently support rendering of high resolution images under zone rendering. In particular, a bin array rectangle and binner clipping rectangle for determining primitive-zone intersections. Both of these rectangles are defined by graphics device state variables containing the screen-space location of the rectangle corners. In particular, the binner clipping rectangle is used to define the visible region in screen coordinates. Objects completely outside the binner clipping rectangle in one or more directions will be discarded. Objects that cannot be trivially rejected are subjected to bin determination. The bin array rectangle handles color buffer resolutions larger than could otherwise be accommodated by the optimally-renderer image limits.
摘要翻译：本发明的实施例有效地支持在区域渲染下渲染高分辨率图像。特别地，用于确定原始区域交叉的bin数组矩形和折边裁剪矩形。这两个矩形由包含矩形角的屏幕空间位置的图形设备状态变量定义。特别地，使用折边裁剪矩形来定义屏幕坐标中的可见区域。完全在一个或多个方向的折边裁剪矩形外的物体将被丢弃。不能平凡拒绝的对象将进行仓确定。 bin数组矩形处理颜色缓冲区分辨率大于否则可以通过最佳渲染器图像限制来适应。

23. 发明申请

US20160086299A1 Position-Only Shading Pipeline 有权
标题翻译：仅定位着色管道
公开(公告)号：US20160086299A1
公开(公告)日：2016-03-24
申请号：US14494653
申请日：2014-09-24
申请人： Saurabh Sharma , Subramaniam Maiyuran , Thomas A. Piazza , Kalyan K. Bhiravabhatla , Peter L. Doyle , Paul A. Johnson , Bimal Poddar , Jon N. Hasselgren , Carl J. Munkberg , Tomas G. Akenine-Moller , Harri Syrja , Kevin Rogovin , Robert L. Farrell
发明人： Saurabh Sharma , Subramaniam Maiyuran , Thomas A. Piazza , Kalyan K. Bhiravabhatla , Peter L. Doyle , Paul A. Johnson , Bimal Poddar , Jon N. Hasselgren , Carl J. Munkberg , Tomas G. Akenine-Moller , Harri Syrja , Kevin Rogovin , Robert L. Farrell
IPC分类号： G06T1/20 , G06T15/40
CPC分类号： G06T1/20 , G06T15/40 , G06T15/405 , G06T15/503 , G09G5/393
摘要： In position-only shading, two geometry pipes exist, a trimmed down version called the Cull Pipe and a full version called the Replay Pipe. Thus, the Cull Pipe executes the position shaders in parallel with the main application, but typically generates the critical results much faster as it fetches and shades only the position attribute of the vertices and avoids the rasterization as well as the rendering of pixels for the frame buffer. Furthermore, the Cull Pipe uses these critical results to compute visibility information for all the triangles whether they are culled or not. On the other hand, the Replay Pipe consumes the visibility information to skip the culled triangles and shades only the visible triangles that are finally passed to the rasterization phase. Together the two pipes can hide the long cull runs of discarded triangles and can complete the work faster in some embodiments.
摘要翻译：在仅位置阴影中，存在两个几何管道，一个称为Cull管道的修剪版本以及称为Replay Pipe的完整版本。因此，Cull管道与主应用程序并行执行位置着色器，但是通常会生成关键结果的速度要快得多，因为它仅获取和仅阴影顶点的位置属性，并避免光栅化以及帧的像素渲染缓冲。此外，Cull管道使用这些关键结果来计算所有三角形的可见性信息，无论它们是否被淘汰。另一方面，重放管道消耗可见性信息来跳过被剔除的三角形，并仅遮蔽最终传递到光栅化阶段的可见三角形。两个管道一起可以隐藏丢弃的三角形的长的剔除运行，并且在一些实施例中可以更快地完成工作。

24. 发明授权

US09064336B2 Multiple texture compositing 有权
标题翻译：多重纹理合成
公开(公告)号：US09064336B2
公开(公告)日：2015-06-23
申请号：US11895382
申请日：2007-08-24
申请人： Kam Leung , Val G. Cook , Peter L. Doyle , Wing Hang Wong
发明人： Kam Leung , Val G. Cook , Peter L. Doyle , Wing Hang Wong
IPC分类号： G09G5/00 , G06T15/04 , G06T11/00 , G06T15/00
CPC分类号： G06T15/04 , G06T11/001 , G06T15/005
摘要： A machine readable storage media containing executable program instructions which when executed cause a digital processing system to set a plurality of operands and operators. A plurality of texture maps are sent to a processor for texture compositing. Operands are selected for a texture operation. A first logic is used wherein if the circulation of blend stages is equal to a number of blend stages, then a color saturation is performed, and a second logic that if the circulation number of blend stages does not equal the number of blend stages then at least one operand is selected for another texture compositing operation.
摘要翻译：一种包含可执行程序指令的机器可读存储介质，其在被执行时使数字处理系统设置多个操作数和操作符。将多个纹理贴图发送到处理器以进行纹理合成。为纹理操作选择操作数。使用第一逻辑，其中如果混合阶段的循环等于混合阶段的数量，则执行颜色饱和度，以及第二逻辑，如果混合阶段的循环数量不等于混合阶段的数量，则在为另一个纹理合成操作选择最少一个操作数。

25. 发明申请

US20140306949A1 SCALABLE GEOMETRY PROCESSING WITHIN A CHECKERBOARD MULTI-GPU CONFIGURATION 有权
标题翻译：在检查板多GPU配置中进行可扩展的几何处理
公开(公告)号：US20140306949A1
公开(公告)日：2014-10-16
申请号：US13976843
申请日：2011-11-18
申请人： Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
发明人： Peter L. Doyle , Jeffery S. Boles , Arthur D. Hunter Jr. , Altug Koker , Aditya Navale
IPC分类号： G06T1/20 , G06T15/10 , G06T15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/10 , G06T2200/28 , G06T2210/52
摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.
摘要翻译：描述了系统，装置和方法，包括将批量的几何对象分发到多核系统，在每个处理器核心处，对相应批次的几何对象执行顶点处理和几何设置处理，将顶点处理结果存储到所有可访问的共享存储器的核心，并将几何设置处理结果存储在本地存储中。然后，每个特定核心可以使用从特定核心内的本地存储器获得的几何设置结果以及至少一个其他处理器核心的本地存储来执行光栅化。

26. 发明申请

US20140139512A1 Recording the Results of Visibility Tests at the Input Geometry Object Granularity 有权
标题翻译：记录输入几何对象粒度的可见性测试结果
公开(公告)号：US20140139512A1
公开(公告)日：2014-05-22
申请号：US13682967
申请日：2012-11-21
申请人： Thomas A. Piazza , Bimal Poddar , Peter L. Doyle
发明人： Thomas A. Piazza , Bimal Poddar , Peter L. Doyle
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T15/40
摘要： According to some embodiments of the present invention, pixel throughput may be improved by performing depth tests and recording the results on the granularity of an input geometry object. An input geometry object is any object within the depiction represented by a primitive, such as a triangle within an input triangle list or a patch within an input patch list.
摘要翻译：根据本发明的一些实施例，可以通过执行深度测试并将结果记录在输入几何对象的粒度上来改善像素吞吐量。输入几何对象是由基元表示的描绘内的任何对象，例如输入三角形列表中的三角形或输入修补程序列表中的修补程序。

27. 发明授权

US06950108B2 Bandwidth reduction for rendering using vertex data 失效
标题翻译：使用顶点数据进行渲染的带宽减少
公开(公告)号：US06950108B2
公开(公告)日：2005-09-27
申请号：US10856054
申请日：2004-05-27
申请人： Peter L. Doyle , Thomas A. Piazza
发明人： Peter L. Doyle , Thomas A. Piazza
IPC分类号： G06T1/60 , G06T15/00 , G09G5/37 , G06F12/02
CPC分类号： G06T1/60 , G06T15/005
摘要： Embodiments of the present invention provide a split vertex buffer where the data for each vertex is split between parallel vertex buffers. The first buffer contains vertex X and Y data, while the second parallel buffer contains the remainder of the vertex data. Given the split vertex buffers, the hardware binning-engine is now permitted to read and cache only vertex screen X and Y data. Especially given a typically high level of temporal coherency between indexed vertex references, the reading and caching of large parcels of vertex screen-space X and Y leads to lower and highly efficient utilization of memory bandwidth for hardware binning input. Embodiments of the present invention thus reduce the hardware binning memory bandwidth requirements and improve memory utilization.
摘要翻译：本发明的实施例提供一种分割顶点缓冲器，其中每个顶点的数据在平行顶点缓冲器之间分割。第一个缓冲区包含顶点X和Y数据，而第二个并行缓冲区包含顶点数据的其余部分。给定分割顶点缓冲区，现在允许硬件分箱引擎读取和缓存顶点屏幕X和Y数据。特别是考虑到索引顶点参考之间通常具有高水平的时间一致性，大块顶点屏幕空间X和Y的读取和高速缓存导致硬件分档输入的存储器带宽的较低和高效利用。因此，本发明的实施例减少了硬件分组存储器带宽需求并提高了存储器利用率。

28. 发明授权

US06747657B2 Depth write disable for zone rendering 有权
公开(公告)号：US06747657B2
公开(公告)日：2004-06-08
申请号：US10038814
申请日：2001-12-31
申请人： Peter L. Doyle , Aditya Sreenivas
发明人： Peter L. Doyle , Aditya Sreenivas
IPC分类号： G06F1300
CPC分类号： G06T1/60 , G06T15/405
摘要： A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

29. 发明授权

US06738069B2 Efficient graphics state management for zone rendering 有权
标题翻译：区域渲染的高效图形状态管理
公开(公告)号：US06738069B2
公开(公告)日：2004-05-18
申请号：US10039007
申请日：2001-12-31
申请人： Peter L. Doyle
发明人： Peter L. Doyle
IPC分类号： G09G536
CPC分类号： G06T15/005
摘要： The present invention provides a mechanism to track and manage graphics state with hardware state-binning logic for use with the tile-based zone rendering method of generating graphical images. Only the current values of the dynamic state variables are maintained in hardware. Dynamic includes, but is not limited to, state variables that are considered likely to change between primitives. The set of dynamic state variables is subdivided into subgroups. Each state group is associated with a per-bin array of tracking bits. Whenever a state change is encountered, the tracking bit corresponding to the associated state group is set for all bins. Prior to placing a primitive in a bin, the tracking bits associated with that bin are examined, and the current state corresponding to set tracking bits is inserted in the bin before the primitive. Then the tracking bits for that bin are cleared.
摘要翻译：本发明提供一种用于利用硬件状态分级逻辑来跟踪和管理图形状态的机制，以用于生成图形图像的基于瓦片的区域渲染方法。只有硬件中维护动态状态变量的当前值。动态包括但不限于被认为可能在原语之间变化的状态变量。一组动态状态变量被细分为子组。每个状态组与跟踪位的每个二进制数组相关联。每当遇到状态改变时，对应于相关联的状态组的跟踪位都设置为所有存储区。在将原语放在一个bin之前，检查与该bin相关联的跟踪位，并将与设置的跟踪位对应的当前状态插入到该原语前的bin中。然后清除该仓的跟踪位。

30. 发明授权

US06429873B1 Addressing of monolithic texture maps 有权
标题翻译：解决单片纹理贴图
公开(公告)号：US06429873B1
公开(公告)日：2002-08-06
申请号：US09474182
申请日：1999-12-29
申请人： Nicolas I. Kacevas , Val G. Cook , Peter L. Doyle
发明人： Nicolas I. Kacevas , Val G. Cook , Peter L. Doyle
IPC分类号： G06T1140
CPC分类号： G06T15/04
摘要： A method and circuit for determining the address of texture maps in memory, when only the base address of the primary texture map is known. The various maps associated with a given texture are sized and stored in a manner that allows any texel in any of the maps to be located based on the map number and the base address of the primary map. A circuit is provided that determines the necessary addresses with minimal calculations.
摘要翻译：当只知道主纹理图的基地址时，用于确定存储器中纹理贴图的地址的方法和电路。与给定纹理相关联的各种地图的大小和存储方式允许根据地图编号和主地图的基地址来定位任何地图中的任何纹理。提供了一种电路，通过最少的计算确定必要的地址。

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